Rational Function Interpolation of Electromagnetic Transfer Functions of High-Speed Interconnect Systems from Discrete Time-Domain and Frequency-Domain Data

We present new methodologies to generate rational function approximations of broadband electromagnetic responses of linear and passive networks of high-speed interconnects, and to construct SPICE-compatible, equivalent circuit representations of the generated rational functions. These new methodologies are driven by the desire to improve the computational efficiency of the rational function fitting process, and to ensure enhanced accuracy of the generated rational function interpolation and its equivalent circuit representation. Toward this goal, we propose two new methodologies for rational function approximation of high-speed interconnect network responses. The first one relies on the use of both time-domain and frequency-domain data, obtained either through measurement or numerical simulation, to generate a rational function representation that extrapolates the input, early-time transient response data to late-time response while at the same time providing a means to both interpolate and extrapolate the used frequency-domain data. The aforementioned hybrid methodology can be considered as a generalization of the frequency-domain rational function fitting utilizing frequency-domain response data only, and the time-domain rational function fitting utilizing transient response data only. In this context, a guideline is proposed for estimating the order of the rational function approximation from transient data. The availability of such an estimate expedites the time-domain rational function fitting process. The second approach relies on the extraction of the delay associated with causal electromagnetic responses of interconnect systems to provide for a more stable rational function process utilizing a lower-order rational function interpolation. A distinctive feature of the proposed methodology is its utilization of scattering parameters. For both methodologies, the approach of fitting the electromagnetic network matrix one element at a time is applied. It is shown that, with regard to the computational cost of the rational function fitting process, such an element-by-element rational function fitting is more advantageous than full matrix fitting for systems with a large number of ports. Despite the disadvantage that different sets of poles are used in the rational function of different elements in the network matrix, such an approach provides for improved accuracy in the fitting of network matrices of systems characterized by both strongly coupled and weakly coupled ports. Finally, in order to provide a means for enforcing passivity in the adopted element-by-element rational function fitting approach, the methodology for passivity enforcement via quadratic programming is modified appropriately for this purpose and demonstrated in the context of element-by-element rational function fitting of the admittance matrix of an electromagnetic multiport.

Application of the latency insertion method (LIM) to the analysis of large circuit interconnect networks

The focus of this research is to explore the applications of the finite difference formulation based on the latency insertion method (LIM) to the analysis of circuit interconnects. Special attention is devoted to addressing the issues that arise in very large networks such as on-chip signal and power distribution networks. We demonstrate that the LIM has the power and flexibility to handle various types of analysis required at different stages of circuit design. The LIM is particularly suitable for simulations of very large scale linear networks and can significantly outperform conventional circuit solvers (such as SPICE).

Contextualising the teaching and learning of measurement within Torres Strait Islander schools

A one year mathematics project that focused on measurement was conducted with six Torres Strait Islander schools and communities. Its key focus was to contextualise the teaching and learning of measurement within the students’ culture, communities and home languages. There were six teachers and two teacher aides who participated in the project. This paper reports on the findings from the teachers’ and teacher aides’ survey questionnaire used in the first Professional Development session to identify: a) teachers’ experience of teaching in Torres Strait Islands, b) teachers’ beliefs about effective ways to teach Torres Strait Islander students, and c) contexualising measurement within Torres Strait Islander culture, Communities and home languages. A wide range of differing levels of knowledge and understanding about how to contextualise measurement to support student learning were identified and analysed. For example, an Indigenous teacher claimed that mathematics and the environment are relational, that is, they are not discrete and in isolation from one another, rather they interconnect with mathematical ideas emerging from the environment of the Torres Strait Communities.

Collaboration based on web services

Web services are software components designed to support interoperable machine-to-machine interactions over a network, through the exchange of SOAP messages. Since the underlying technology is independent of any specific programming language, Web Services can be effectively used to interconnect business processes across different organizations. However, a standard way of representing such interconnections has not yet emerged and is the subject of an ongoing debate.

Xiamen Hai Cang tourism project : landscape planning and design of five islands

International practice-led design research in landscape architecture has identified the need for addressing the loss of biodiversity in urban environments. China has lost much of its biodiversity in rural and urban environments over thousands of years. However some Chinese cities have attempted to conserve what remains and enhance existing vegetation communities in isolated pockets. Island biogeography has been used as the basis for planning and designing landscapes in Australia and North America but not as yet in China, as far as we know. A gap in landscape design knowledge exists regarding how to apply landscape ecology concepts to urban islands of remaining biodiversity being developed for heavy Chinese domestic tourism impacts in the future. This project responded to the demands for harbour-side tourism opportunities in Xiamen City, Fujian Province, by proposing a range of eco-design innovations using concepts of patch, edge and interior to interconnect people and nature in a Chinese setting.

Generator interconnection procedures at the Midwest ISO

The Midwestern US is a wind-rich resource and wind power is being developed in this region at a very brisk pace. Transporting this energy resource to load centers invariably requires massive transmission lines. This issue of developing additional transmission to support reliable integration of wind on to the power grid provides a multitude of interesting challenges spanning various areas of power systems such as transmission planning, real-time operations and cost-allocation for new transmission. The Midwest ISO as a regional transmission provider is responsible for processing requests to interconnect proposed generation on to the transmission grid under its purview. This paper provides information about some of the issues faced in performing interconnection planning studies and Midwest ISO's efforts to improve its generator interconnection procedures. Related cost-allocation efforts currently ongoing at the Midwest ISO to streamline integration of bulk quantities of wind power in to the transmission grid are also presented.

A LIN inspired optical bus for signal isolation in multilevel or modular power electronic converters

Proposed in this paper is a low-cost, half-duplex optical communication bus for control signal isolation in modular or multilevel power electronic converters. The concept is inspired by the Local Interconnect Network (LIN) serial network protocol as used in the automotive industry. The proposed communications bus utilises readily available optical transceivers and is suitable for use with low-cost microcontrollers for distributed control of multilevel converters. As a signal isolation concept, the proposed optical bus enables very high cell count modular multilevel cascaded converters (MMCCs) for high-bandwidth, high-voltage and high-power applications. Prototype hardware is developed and the optical bus concept is validated experimentally in a 33-level MMCC converter operating at 120 Vrms and 60 Hz.

Latency, Power and Performance Trade-offs in Network-on-Chips by Link Microarchitecture Exploration

This paper presents a power, latency and throughput trade-off study on NoCs by varying microarchitectural (e.g. pipelining) and circuit level (e.g. frequency and voltage) parameters. We change pipelining depth, operating frequency and supply voltage for 3 example NoCs - 16 node 2D Torus, Tree network and Reduced 2D Torus. We use an in-house NoC exploration framework capable of topology generation and comparison using parameterized models of Routers and links developed in SystemC. The framework utilizes interconnect power and delay models from a low-level modelling tool called Intacte[1]1. We find that increased pipelining can actually reduce latency. We also find that there exists an optimal degree of pipelining which is the most energy efficient in terms of minimizing energy-delay product.

Kirjan tie lukijalle : Kirjakauppojen vakiintuminen Suomessa 1740 - 1860

Books Paths to Readers describes the history of the origins and consolidation of modern and open book stores in Finland 1740 1860. The thesis approaches the book trade as a part of a print culture. Instead of literary studies choice to concentrate on texts and writers, book history seeks to describe the print culture of a society and how the literary activities and societies interconnect. For book historians, printed works are creations of various individuals and groups: writers, printers, editors, book sellers, censors, critics and finally, readers. They all take part in the creation, delivery and interpretation of printed works. The study reveals the ways selling and distributing books have influenced the printed works and the literary and print culture. The research period 1740 1860 covers the so-called second revolution of the book, or the modernisation of the print culture. The thesis describes the history of 60 book stores and their 96 owners. The study concentrates on three themes: firstly, how the particular book trade network became a central institution for printed works distribution, secondly what were the relations between cosmopolitan European book markets and the national cultural sphere, and thirdly how book stores functioned as cultural institutions and business enterprises. Book stores that have a varied assortment and are targeted to all readers became the main institution for book trade in Finland during 1740 1860. It happened because of three features. First, the book binders monopoly on selling bound copies in Sweden was abolished in 1740s. As a consequence entrepreneurs could concentrate solely to trade activities and offer copies from various publishers at their stores. Secondly the common business model of bartering was replaced by selling copies for cash, first in the German book trade centre Leipzig in 1770s. The change intensified book markets activities and Finnish book stores foreign connections. Thirdly, after Finland was annexed to the Russian empire in 1809, the Grand duchy s administration steered foreign book trade to book stores (because of censorship demands). Up to 1830 s book stores were available only in Helsinki and Turku. During next ten years book stores opened in six regional centres. The early entrepreneurs ran usually vertical businesses consisting of printing, publishing and distribution activities. This strategy lowered costs, eased the delivery of printed works and helped to create elaborated centres for all book activities. These book stores main clientele consisted of the Swedish speaking gentry. During late 1840s various opinion leaders called for the development of a national Finnish print culture, and also book stores. As a result, during the five years before the beginning of the Crimean war (1853 1856) book stores were opened in almost all Finnish towns: at the beginning of the war 36 book stores operated in 21 towns. The later book sellers, mainly functioning in small towns among Finnish speaking people, settled usually strictly for selling activities. Book stores received most of their revenues from selling foreign titles. Swedish, German, French and Belgian (pirate editions of popular French novels) books were widely available for the multilingual gentry. Foreign titles and copies brought in most of the revenues. Censorship inspections or unfavourable custom fees would not limit the imports. Even if the local Finnish print production steadily rose, many copies, even titles, were never delivered via book stores. Only during the 1840 s and 1850 s the most advanced publishers would concentrate on creating publishing programmes and delivering their titles via book stores. Book sellers regulated commissions were small. They got even smaller because of large amounts of unsold copies, various and usual misunderstandings of consignments and accounts or plain accidents that destroyed shipments and warehouses. Also, the cultural aim of a creating large and assortments and the tendency of short selling periods demanded professional entrepreneurship, which many small town book sellers however lacked. In the midst of troublesome business efforts, co-operation and mutual concern of the book market s entrepreneurs were the key elements of the trade, although on local level book sellers would compete, sometimes even ferociously. The difficult circumstances (new censorship decree of 1850, Crimean war) and lack of entrepreneurship, experience and customers meant that half of the book stores opened in 1845 1860 was shut in less than five years. In 1858 the few leading publishers established The Finnish Book Publishers Association. Its first task was to create new business rules and manners for the book trade. The association s activities began to professionalise the whole network, but at the same time the earlier independence of regional publishing and selling enterprises diminished greatly. The consolidation of modern and open book store network in Finland is a history of a slow and complex development without clear signs of a beginning or an end. The ideal book store model was rarely accomplished in its all features. Nevertheless, book stores became the norm of the book trade. They managed to offer larger selections, reached larger clienteles and maintained constant activity better than any other book distribution model. In essential, the book stores methods have not changed up to present times.

X-ray Studies on Crystalline Complexes Involving Amino Acids and Peptides. XIII. Effect of Chirality on Molecular Aggregation: The Crystal Structures of L-Arginine D-Aspartate and L-Arginine D-Glutamate Trihydrate

The crystal structures of (1) L-arginine D-asparate, C6HIsN40~.C4H6NO4 [triclinic, P1, a=5.239(1), b=9.544(1), c=14.064(2)A, a=85"58(1), /3=88.73 (1), ~/=84.35 (1) °, Z=2] and (2) L-arginine D-glutamate trihydrate, C6H15N40~-.CsHsNO4.3H20 [monoclinic, P2~, a=9.968(2), b=4.652(1), c=19.930 (2) A, fl = 101.20 (1) °, Z = 2] have been determined using direct methods. They have been refined to R =0.042 and 0.048 for 2829 and 2035 unique reflections respectively [I>2cr(I)]. The conformations of the two arginine molecules in the aspartate complex are different from those observed so far in the crystal structures of arginine, its salts and complexes. In both complexes, the molecules are organized into double layers stacked along the longest axis. The core of each double layer consists of two parallel sheets made up of main-chain atoms, each involving both types of molecules. The hydrogen bonds within each sheet and those that interconnect the two sheets give rise to EL-, DD- and DE-type head-to-tail sequences. Adjacent double layers in (1) are held together by side-chain-side-chain interactions whereas those in (2) are interconnected through an extensive network of water molecules which interact with sidechain guanidyl and carboxylate groups. The aggregation pattern observed in the two LD complexes is fundamentally different from that found in the corresponding EL complexes.

Redefine: Runtime Reconfigurable Polymorphic ASIC

Emerging embedded applications are based on evolving standards (e.g., MPEG2/4, H.264/265, IEEE802.11a/b/g/n). Since most of these applications run on handheld devices, there is an increasing need for a single chip solution that can dynamically interoperate between different standards and their derivatives. In order to achieve high resource utilization and low power dissipation, we propose REDEFINE, a polymorphic ASIC in which specialized hardware units are replaced with basic hardware units that can create the same functionality by runtime re-composition. It is a ``future-proof'' custom hardware solution for multiple applications and their derivatives in a domain. In this article, we describe a compiler framework and supporting hardware comprising compute, storage, and communication resources. Applications described in high-level language (e.g., C) are compiled into application substructures. For each application substructure, a set of compute elements on the hardware are interconnected during runtime to form a pattern that closely matches the communication pattern of that particular application. The advantage is that the bounded CEs are neither processor cores nor logic elements as in FPGAs. Hence, REDEFINE offers the power and performance advantage of an ASIC and the hardware reconfigurability and programmability of that of an FPGA/instruction set processor. In addition, the hardware supports custom instruction pipelining. Existing instruction-set extensible processors determine a sequence of instructions that repeatedly occur within the application to create custom instructions at design time to speed up the execution of this sequence. We extend this scheme further, where a kernel is compiled into custom instructions that bear strong producer-consumer relationship (and not limited to frequently occurring sequences of instructions). Custom instructions, realized as hardware compositions effected at runtime, allow several instances of the same to be active in parallel. A key distinguishing factor in majority of the emerging embedded applications is stream processing. To reduce the overheads of data transfer between custom instructions, direct communication paths are employed among custom instructions. In this article, we present the overview of the hardware-aware compiler framework, which determines the NoC-aware schedule of transports of the data exchanged between the custom instructions on the interconnect. The results for the FFT kernel indicate a 25% reduction in the number of loads/stores, and throughput improves by log(n) for n-point FFT when compared to sequential implementation. Overall, REDEFINE offers flexibility and a runtime reconfigurability at the expense of 1.16x in power and 8x in area when compared to an ASIC. REDEFINE implementation consumes 0.1x the power of an FPGA implementation. In addition, the configuration overhead of the FPGA implementation is 1,000x more than that of REDEFINE.

Recent advances in radar technology

The technical developments and advances that have taken place thus far are reviewed in those areas impacting future phased array active aperture radar systems. The areas covered are printed circuit antennas and antenna arrays, GaAs MMIC design and fabrication leading to affordable transmitter-receiver (T-R) modules, and novel hardware and software developments. The use of fiber-optic distribution networks to interconnect the monolithically integrated optical components with the T-R modules is discussed. Beamforming and sidelobe control techniques for active phased array systems are also examined.

Queuing strategies for qos management of traffic between lans interconnected by low-speed wan links

We provide a comparative performance evaluation of packet queuing and link admission strategies for low-speed wide area network Links (e.g. 9600 bps, 64 kbps) that interconnect relatively highspeed, connectionless local area networks (e.g. 10 Mbps). In particular, we are concerned with the problem of providing differential quality of service to interLAN remote terminal and file transfer sessions, and throughput fairness between interLAN file transfer sessions. We use analytical and simulation models to study a variety of strategies. Our work also serves to address the performance comparison of connectionless vs. connection-oriented interconnection of CLNS LANS. When provision of priority at the physical transmission level is not feasible, we show, for low-speed WAN links (e.g. 9600 bps), the superiority of connection-oriented interconnection of connectionless LANs, with segregation of traffic streams with different QoS requirements into different window flow controlled connections. Such an implementation can easily be obtained by transporting IP packets over an X.25 WAN. For 64 kbps WAN links, there is a drop in file transfer throughputs, owing to connection overheads, but the other advantages are retained, The same solution also helps to provide throughput fairness between interLAN file transfer sessions. We also provide a corroboration of some of our modelling results with results from an experimental test-bed.

Accelerating multi-core simulators

Simulation is an important means of evaluating new microarchitectures. With the invention of multi-core (CMP) platforms, simulators are becoming larger and more complex. However, with the availability of CMPs with larger caches and higher operating frequency, the wall clock time required for simulating an application has become comparatively shorter. Reducing this simulation time further is a great challenge, especially in the case of multi-threaded workload due to indeterminacy introduced due to simultaneously executing various threads. In this paper, we propose a technique for speeding multi-core simulation. The model of the processor core and cache are replaced with functional models, to achieve speedup. A timed Petri net model is used to estimate the execution time of the processor and the memory access latencies are estimated using hit/miss information obtained from the functional model of the cache. This model can be used to predict performance of data parallel applications or multiprogramming workload on CMP platform with various cache hierarchies and shared bus interconnect. The error in estimation of the execution time of an application is within 6%. The speedup achieved ranges between an average of 2x--4x over the cycle accurate simulator.

Exploiting Programmable Network Interfaces for Parallel Query Execution in Workstation Clusters

Workstation clusters equipped with high performance interconnect having programmable network processors facilitate interesting opportunities to enhance the performance of parallel application run on them. In this paper, we propose schemes where certain application level processing in parallel database query execution is performed on the network processor. We evaluate the performance of TPC-H queries executing on a high end cluster where all tuple processing is done on the host processor, using a timed Petri net model, and find that tuple processing costs on the host processor dominate the execution time. These results are validated using a small cluster. We therefore propose 4 schemes where certain tuple processing activity is offloaded to the network processor. The first 2 schemes offload the tuple splitting activity - computation to identify the node on which to process the tuples, resulting in an execution time speedup of 1.09 relative to the base scheme, but with I/O bus becoming the bottleneck resource. In the 3rd scheme in addition to offloading tuple processing activity, the disk and network interface are combined to avoid the I/O bus bottleneck, which results in speedups up to 1.16, but with high host processor utilization. Our 4th scheme where the network processor also performs apart of join operation along with the host processor, gives a speedup of 1.47 along with balanced system resource utilizations. Further we observe that the proposed schemes perform equally well even in a scaled architecture i.e., when the number of processors is increased from 2 to 64