Field applications of the second-generation Environmental Sample Processor (ESP) for remote detection of harmful algae: 2006-2007

We assess the application of the second-generation Environmental Sample Processor (ESP) for the detection of harmful algal bloom (HAB) species in field and laboratory settings using two molecular probe techniques: a sandwich hybridization assay (SHA) and fluorescent in situ hybridization (FISH). During spring 2006, the first time this new instrument was deployed, the ESP successfully automated application of DNA probe arrays for various HAB species and other planktonic taxa, but non-specific background binding on the SHA probe array support made results interpretation problematic. Following 2006, the DNA array support membrane that we were using was replaced with a different membrane, and the SHA chemistry was adjusted. The sensitivity and dynamic range of these modifications were assessed using 96-well plate and ESP array SHA formats for several HAB species found commonly in Monterey Bay over a range of concentrations; responses were significantly correlated (p < 0.01). Modified arrays were deployed in 2007. Compared to 2006, probe arrays showed improved signal:noise, and remote detection of various HAB species was demonstrated. We confirmed that the ESP and affiliated assays can detect HAB populations at levels below those posing human health concerns, and results can be related to prevailing environmental conditions in near real-time.

A single all-optical processor for multiple spectral amplitude code label recognition using four wave mixing

We propose a novel label processor which can recognize multiple spectral-amplitude-code labels using four-wave-mixing sidebands and selective optical filtering. Ten code-labels x 10 Gbps variable-length packets are transmitted over a 200 km single-hop switched network.

A low latency optical top of rack switch for data centre networks with minimized processor energy load

We propose a low latency optical data center top of rack switch using recirculation buffering and a hybrid MZ/SOA switch architecture to reduce the network power dissipated on future optically connected server chips by 53%. © OSA 2014.

Performance of an embedded optical vector matrix multiplication processor architecture

An embedded architecture of optical vector matrix multiplier (OVMM) is presented. The embedded architecture is aimed at optimising the data flow of vector matrix multiplier (VMM) to promote its performance. Data dependence is discussed when the OVMM is connected to a cluster system. A simulator is built to analyse the performance according to the architecture. According to the simulation, Amdahl's law is used to analyse the hybrid opto-electronic system. It is found that the electronic part and its interaction with optical part form the bottleneck of system.

虚拟硬件方法实现基于Intel StrongARM SA-1110平台的Linux APM

文章讨论了在StrongARM SA－1110开发板上实现Linux APM的主要技术问题。在分析了Intel StrongARM最新处理器SA－1110及开发板（Assabet）与电源管理相关的结构和特性的基础上，提出了一种基于虚拟硬件的系统跨平台移植的方法和思路，并以实际开发过程中的经验为背景，介绍了在Linux APM基于SA－1110平台的移植工作中虚拟硬件方法的应用和虚拟硬件方法在操作系统跨平台移植开发上的优点。

Intel 8279芯片在8位和16位米字LED显示电路中的应用

本文简要介绍了16段米字LED字符管的动态扫描，以及通用显示和键盘接口器件Intel8279芯片的显示接口结构和功能，讨论了通过一定的附加电路来扩展Intel8279的显示功能，使之控制8位和16位的米字LED字符管的动态显示，并结合两种具体的硬件电路和程序，说明了两种方案的实现方法和工作原理。

Message-Driven Processor Architecture: Verson 11

The Message-Driven Processor is a node of a large-scale multiprocessor being developed by the Concurrent VLSI Architecture Group. It is intended to support fine-grained, message passing, parallel computation. It contains several novel architectural features, such as a low-latency network interface, extensive type-checking hardware, and on-chip memory that can be used as an associative lookup table. This document is a programmer's guide to the MDP. It describes the processor's register architecture, instruction set, and the data types supported by the processor. It also details the MDP's message sending and exception handling facilities.

Cellular automata and non-static image processing for embodied robot systems on a massively parallel processor array

Huelse, M, Barr, D R W, Dudek, P: Cellular Automata and non-static image processing for embodied robot systems on a massively parallel processor array. In: Adamatzky, A et al. (eds) AUTOMATA 2008, Theory and Applications of Cellular Automata. Luniver Press, 2008, pp. 504-510. Sponsorship: EPSRC

A fast, streaming SIMD extensions 2, logistic squashing function

Schraudolph proposed an excellent exponential approximation providing increased performance particularly suited to the logistic squashing function used within many neural networking applications. This note applies Intel's streaming SIMD Extensions 2 (SSE2), where SIMD is single instruction multiple data, of the Pentum IV class processor to Schraudolph's technique, further increasing the performance of the logistic squashing function. It was found that the calculation of the new 32-bit SSE2 logistic squashing function described here was up to 38 times faster than the conventional exponential function and up to 16 times faster than a Schraudolph-style 32-bit method on an Intel Pentum D 3.6 GHz CPU.

Generic SoC QR Array Processor for Adaptive Beamforming

A generic architecture for implementing a QR array processor in silicon is presented. This improves on previous research by considerably simplifying the derivation of timing schedules for a QR system implemented as a folded linear array, where account has to be taken of processor cell latency and timing at the detailed circuit level. The architecture and scheduling derived have been used to create a generator for the rapid design of System-on-a-Chip (SoC) cores for QR decomposition. This is demonstrated through the design of a single-chip architecture for implementing an adaptive beamformer for radar applications. Published as IEEE Trans Circuits and Systems Part II, Analog and Digital Signal Processing, April 2003 NOT Express Briefs. Parts 1 and II of Journal reorganised since then into Regular Papers and Express briefs

Application-Specific Instruction Set Processor for SoC implementation of Modern Signal Processing Algorithms

A novel application-specific instruction set processor (ASIP) for use in the construction of modern signal processing systems is presented. This is a flexible device that can be used in the construction of array processor systems for the real-time implementation of functions such as singular-value decomposition (SVD) and QR decomposition (QRD), as well as other important matrix computations. It uses a coordinate rotation digital computer (CORDIC) module to perform arithmetic operations and several approaches are adopted to achieve high performance including pipelining of the micro-rotations, the use of parallel instructions and a dual-bus architecture. In addition, a novel method for scale factor correction is presented which only needs to be applied once at the end of the computation. This also reduces computation time and enhances performance. Methods are described which allow this processor to be used in reduced dimension (i.e., folded) array processor structures that allow tradeoffs between hardware and performance. The net result is a flexible matrix computational processing element (PE) whose functionality can be changed under program control for use in a wider range of scenarios than previous work. Details are presented of the results of a design study, which considers the application of this decomposition PE architecture in a combined SVD/QRD system and demonstrates that a combination of high performance and efficient silicon implementation are achievable. © 2005 IEEE.