Memory Hierarchy Hardware-Software Co-design in Embedded Systems

The memory hierarchy is the main bottleneck in modern computer systems as the gap between the speed of the processor and the memory continues to grow larger. The situation in embedded systems is even worse. The memory hierarchy consumes a large amount of chip area and energy, which are precious resources in embedded systems. Moreover, embedded systems have multiple design objectives such as performance, energy consumption, and area, etc. Customizing the memory hierarchy for specific applications is a very important way to take full advantage of limited resources to maximize the performance. However, the traditional custom memory hierarchy design methodologies are phase-ordered. They separate the application optimization from the memory hierarchy architecture design, which tend to result in local-optimal solutions. In traditional Hardware-Software co-design methodologies, much of the work has focused on utilizing reconfigurable logic to partition the computation. However, utilizing reconfigurable logic to perform the memory hierarchy design is seldom addressed. In this paper, we propose a new framework for designing memory hierarchy for embedded systems. The framework will take advantage of the flexible reconfigurable logic to customize the memory hierarchy for specific applications. It combines the application optimization and memory hierarchy design together to obtain a global-optimal solution. Using the framework, we performed a case study to design a new software-controlled instruction memory that showed promising potential.

Immersió guiada en el maquinari dels ordinadors. 'Inmersión guiada en el hardware de los ordenadores'.

Resumen tomado de la publicación. Se adjuntan actividades de consolidación de los contenidos del curso. Incluye imágenes

Administración y control de hardware y software para las medianas y grandes empresas en la ciudad de Bogotá

El bajo costo de los elementos utilizados en computación han permitido que cualquier entidad organizacional pueda dotar a la gran mayoría de sus empleados con herramientas de cómputo. Esto ha generado que la Administración y Control de los elementos

Manteniment d'equips informàtics : maquinari i programari. 'Mantenimiento de equipos informáticos : hardware y software'.

Este documento no está publicado

Open Hardware

Presentació sobre la creació de la placa Arduino, i els projectes que s'han fet arreu amb aquesta placa

Good-visibility computation using graphics hardware

Aquesta tesi tracta del disseny, implementació i discussió d'algoritmes per resoldre problemes de visibilitat i bona-visibilitat utilitzant el hardware gràfic de l'ordinador. Concretament, s'obté una discretització dels mapes de multi-visibilitat i bona-visibilitat a partir d'un conjunt d'objectes de visió i un conjunt d'obstacles. Aquests algoritmes són útils tant per fer càlculs en dues dimensions com en tres dimensions. Fins i tot ens permeten calcular-los sobre terrenys.

A practical method for testing high-speed networking hardware architectures

This paper deals with the key issues encountered in testing during the development of high-speed networking hardware systems by documenting a practical method for "real-life like" testing. The proposed method is empowered by modern and commonly available Field Programmable Gate Array (FPGA) technology. Innovative application of standard FPGA blocks in combination with reconfigurability are used as a back-bone of the method. A detailed elaboration of the method is given so as to serve as a general reference. The method is fully characterised and compared to alternatives through a case study proving it to be the most efficient and effective one at a reasonable cost.

A compositional framework for hardware/software co-design

We describe a compositional framework, together with its supporting toolset, for hardware/software co-design. Our framework is an integration of a formal approach within a traditional design flow. The formal approach is based on Interval Temporal Logic and its executable subset, Tempura. Refinement is the key element in our framework because it will derive from a single formal specification of the system the software and hardware parts of the implementation, while preserving all properties of the system specification. During refinement simulation is used to choose the appropriate refinement rules, which are applied automatically in the HOL system. The framework is illustrated with two case studies. The work presented is part of a UK collaborative research project between the Software Technology Research Laboratory at the De Montfort University and the Oxford University Computing Laboratory.

Hardware development of the Yorick series of active vision systems

This paper presents a review of the design and development of the Yorick series of active stereo camera platforms and their integration into real-time closed loop active vision systems, whose applications span surveillance, navigation of autonomously guided vehicles (AGVs), and inspection tasks for teleoperation, including immersive visual telepresence. The mechatronic approach adopted for the design of the first system, including head/eye platform, local controller, vision engine, gaze controller and system integration, proved to be very successful. The design team comprised researchers with experience in parallel computing, robot control, mechanical design and machine vision. The success of the project has generated sufficient interest to sanction a number of revisions of the original head design, including the design of a lightweight compact head for use on a robot arm, and the further development of a robot head to look specifically at increasing visual resolution for visual telepresence. The controller and vision processing engines have also been upgraded, to include the control of robot heads on mobile platforms and control of vergence through tracking of an operator's eye movement. This paper details the hardware development of the different active vision/telepresence systems.

A specific pole placement technique to minimise hardware requirements within a real time terrestrial and cable video echo canceller

The real time hardware architecture of a deterministic video echo canceller (deghoster) system is presented. The deghoster is capable of calculating all the multipath channel distortion characteristics from terrestrial and cable television in one single pass while performing real time video in-line ghost cancellation. The results from the actual system are also presented in this paper.

A compact low-cost electronic hardware design for actuating soft robots

A low cost, compact embedded design approach for actuating soft robots is presented. The complete fabrication procedure and mode of operation was demonstrated, and the performance of the complete system was also demonstrated by building a microcontroller based hardware system which was used to actuate a soft robot for bending motion. The actuation system including the electronic circuit board and actuation components was embedded in a 3D-printed casing to ensure a compact approach for actuating soft robots. Results show the viability of the system in actuating and controlling siliconebased soft robots to achieve bending motions. Qualitative measurements of uniaxial tensile test, bending distance and pressure were obtained. This electronic design is easy to reproduce and integrate into any specified soft robotic device requiring pneumatic actuation.