Targeting resource investments to achieve sediment reduction and improved Great Barrier Reef health

Concerns about excessive sediment loads entering the Great Barrier Reef (GBR) lagoon in Australia have led to a focus on improving ground cover in grazing lands. Ground cover has been identified as an important factor in reducing sediment loads, but improving ground cover has been difficult for reef stakeholders in major catchments of the GBR. To provide better information an optimising linear programming model based on paddock scale information in conjunction with land type mapping was developed for the Fitzroy, the largest of the GBR catchments. This identifies at a catchment scale which land types allow the most sediment reduction to be achieved at least cost. The results suggest that from the five land types modelled, the lower productivity land types present the cheapest option for sediment reductions. The study allows more informed decision making for natural resource management organisations to target investments. The analysis highlights the importance of efficient allocation of natural resource management funds in achieving sediment reductions through targeted land type investments. © 2012.

A direct borohydride fuel cell employing Prussian Blue as mediated electron-transfer hydrogen peroxide reduction catalyst

A direct borohydride-hydrogen peroxide fuel cell employing carbon-supported Prussian Blue (PB) as mediated electron-transfer cathode catalyst is reported. While operating at 30 °C, the direct borohydride-hydrogen peroxide fuel cell employing carbon-supported PB cathode catalyst shows superior performance with the maximum output power density of 68 mW cm−2 at an operating voltage of 1.1 V compared to direct borohydride-hydrogen peroxide fuel cell employing the conventional gold-based cathode with the maximum output power density of 47 mW cm−2 at an operating voltage of 0.7 V. X-ray diffraction (XRD), Scanning Electron Microscopy (SEM), and Energy Dispersive X-ray Analysis (EDAX) suggest that anchoring of Cetyl-Trimethyl Ammonium Bromide (CTAB) as a surfactant moiety on carbon-supported PB affects the catalyst morphology. Polarization studies on direct borohydride-hydrogen peroxide fuel cell with carbon-supported CTAB-anchored PB cathode exhibit better performance with the maximum output power density of 50 mW cm−2 at an operating voltage of 1 V than the direct borohydride-hydrogen peroxide fuel cell with carbon-supported Prussian Blue without CTAB with the maximum output power density of 29 mW cm−2 at an operating voltage of 1 V.

Field Reduction Electrodes for the Possible Improvement in the Pollution Flashover Performance of Porcelain Insulators

In this paper an attempt is made to study accurately, the field distribution for various types of porcelain/ceramic insulators used forhigh voltage transmission. The surface charge Simulation method is employed for the field computation. Novel field reduction electrodes are developed to reduce the maximum field around the pin region. In order to experimentally scrutinize the performance of discs with field reduction electrodes, special artificial pollution test facility was built and utilized. The experimental results show better improvement in the pollution flashover performance of string insulators.

Reduction of Torque Ripple in Induction Motor Drives Using an AdvancedHybrid PWM Technique

A voltage source inverter-fed induction motor produces a pulsating torque due to application of nonsinusoidal voltages. Torque pulsation is strongly influenced by the pulsewidth modulation (PWM) method employed. Conventional space vector PWM (CSVPWM) is known to result in less torque ripple than sine-triangle PWM. This paper aims at further reduction in the pulsating torque by employing advanced bus-clamping switching sequences, which apply an active vector twice in a subcycle. This paper proposes a hybrid PWM technique which employs such advanced bus-clamping sequences in conjunction with a conventional switching sequence. The proposed hybrid PWM technique is shown to reduce the torque ripple considerably over CSVPWM along with a marginal reduction in current ripple.

Enhancement of Surface Flashover Performance of High Voltage Ceramic Disc Insulators

In this paper, an effort is made to study accurately the field distribution for various types of ceramic insulators used for high-voltage transmission. The surface charge simulation method (SCSM) is employed for the field computation. With the help of SCSM program, a Novel field reduction electrode is designed and developed to reduce the maximum field around the pin region. In order to experimentally analyze the performance of discs with field reduction electrode, special artificial pollution test facility was built and utilized. The experimental results show better surface flashover performance of ceramic insulators used in high-voltage transmission and distribution systems.

Compiler-Directed Dynamic Voltage Scaling using Program Phases

Energy consumption has become a major constraint in providing increased functionality for devices with small form factors. Dynamic voltage and frequency scaling has been identified as an effective approach for reducing the energy consumption of embedded systems. Earlier works on dynamic voltage scaling focused mainly on performing voltage scaling when the CPU is waiting for memory subsystem or concentrated chiefly on loop nests and/or subroutine calls having sufficient number of dynamic instructions. This paper concentrates on coarser program regions and for the first time uses program phase behavior for performing dynamic voltage scaling. Program phases are annotated at compile time with mode switch instructions. Further, we relate the Dynamic Voltage Scaling Problem to the Multiple Choice Knapsack Problem, and use well known heuristics to solve it efficiently. Also, we develop a simple integer linear program formulation for this problem. Experimental evaluation on a set of media applications reveal that our heuristic method obtains a 38% reduction in energy consumption on an average, with a performance degradation of 1% and upto 45% reduction in energy with a performance degradation of 5%. Further, the energy consumed by the heuristic solution is within 1% of the optimal solution obtained from the ILP approach.

The phenomenon of notch in an NEMP simulator and its reduction

The effect of variation in the switching instant of the output switch of the pulser circuit used in energizing an NEMP simulator on the voltage fed to the simulator and hence the electric field within the working volume of the simulator has been studied. Depending upon the instant at which the output switch closes, the amplitude and the wave shape of the voltage that is fed to the illuminator varies. This wave shape of the output voltage from the pulser circuit determines the shape and characteristics of the electric field within the working volume of the simulator. To study the effect of variation in the switching instant on the vertical electric field within the working volume, the vertical electric field has been computed in time and frequency domains. For certain switching instants, the electric field shows a sharp reduction in its amplitude after the peak which is called the notch. The presence of notch results in the test object not getting illuminated with all the frequencies of interest. The notch has been successfully reduced by suitably modifying the pulser circuit.

Voltage and Temperature-Aware SSTA Using Neural Network Delay Model

With the emergence of voltage scaling as one of the most powerful power reduction techniques, it has been important to support voltage scalable statistical static timing analysis (SSTA) in deep submicrometer process nodes. In this paper, we propose a single delay model of logic gate using neural network which comprehensively captures process, voltage, and temperature variation along with input slew and output load. The number of simulation programs with integrated circuit emphasis (SPICE) required to create this model over a large voltage and temperature range is found to be modest and 4x less than that required for a conventional table-based approach with comparable accuracy. We show how the model can be used to derive sensitivities required for linear SSTA for an arbitrary voltage and temperature. Our experimentation on ISCAS 85 benchmarks across a voltage range of 0.9-1.1V shows that the average error in mean delay is less than 1.08% and average error in standard deviation is less than 2.85%. The errors in predicting the 99% and 1% probability point are 1.31% and 1%, respectively, with respect to SPICE. The two potential applications of voltage-aware SSTA have been presented, i.e., one for improving the accuracy of timing analysis by considering instance-specific voltage drops in power grids and the other for determining optimum supply voltage for target yield for dynamic voltage scaling applications.

High voltage DC power supply topology for pulsed load applications with converter switching synchronized to load pulses

High voltage power supplies for radar applications are investigated, which are subjected to pulsed load (125 kHz and 10% duty cycle) with stringent specifications (<0.01% regulation, efficiency>85%, droop<0.5 V/micro-sec.). As good regulation and stable operation requires the converter to be switched at much higher frequency than the pulse load frequency, transformer poses serious problems of insulation failure and higher losses. This paper proposes a methodology to tackle the problems associated with this type of application. Synchronization of converter switching with load pulses enables the converter to switch at half the load switching frequency. Low switching frequency helps in ensuring safety of HV transformer insulation and reduction of losses due to skin and proximity effect. Phase-modulated series resonant converter with ZVS is used as the power converter.

Bypass operation in bridge convertors for high-voltage d.c. transmission

Bypass operation with the aid of a special bypass valve is an important part of present-day schemes of protection for h.v. d.c. transmission systems. In this paper, the possibility of using two valves connected to any phase in the bridge convertor for the purpose of bypass operation is studied. The scheme is based on the use of logic circuits in conjunction with modified methods of fault detection. Analysis of the faults in a d.c. transmission system is carried out with the object of determining the requirements of such a logic-circuit control system. An outline of the scheme for the logic-circuit control of the bypass operation for both rectifier and invertor bridges is then given. Finally, conclusions are drawn regarding the advantages of such a system, which include reduction in the number of valves, prevention of severe faults and fast clearance of faults, in addition to the immediate location of the fault and its nature.

Hypersonic wave drag reduction in re-entry capsules using concentrated energy deposition

Experiments are carried out in a shock tunnel at a nominal Mach number of 5.75 in order to study the effect of concentrated energy deposition on the drag force experienced by a 120° blunt cone. Electrical energy was deposited along the stagnation streamline of the model using a high voltage DC discharge circuit (1.5 – 3.5KW) and the drag force was measured by a single component accelerometer balance. Numerical simulations were also carried complimenting the experiments. These simulations showed a substantial drag reduction (20% ~ 65%) whereas the experiments show no appreciable reduction in drag

Corona treatment for NOx reduction from stationary diesel engine exhaust: Impact of nature of energization and exhaust composition

A detailed study on the removal of oxides of nitrogen (NOx) from the exhaust of a stationary diesel engine was carried out using non-thermal plasma (dielectric barrier discharge) process. The objective of the study was to explore the effect of different voltage energizations and exhaust composition on the NOx removal process. Three types of voltage energizations, namely AC, DC and Pulse were examined. Due to the ease of generation of high voltage AC/DC electrical discharges from automobile/Vehicular battery supply for possible retrofitting in exhaust cleaning circuit, it was found relevant to investigate individual energisation cases in detail for NOx removal. AC and Pulse energisations exhibit a superior NOx removal efficiency compared to DC energisation. However,Pulse energisation is found to be more energy efficient. Experiments were further carried out with filtered/ unfiltered (raw) exhaust under pulse energisations. The results were discussed with regard to NOx removal, energy consumption and formation of by-products.

A nine-level inverter topology for medium-voltage induction motor drive with open-end stator winding

A new scheme for nine-level voltage space-vector generation for medium-voltage induction motor (IM) drives with open-end stator winding is presented in this paper. The proposed nine-level power converter topology consists of two conventional three-phase two-level voltage source inverters powered by isolated dc sources and six floating-capacitor-connected H-bridges. The H-bridge capacitor voltages are effectively maintained at the required asymmetrical levels by employing a space vector modulation (SVPWM) based control strategy. An interesting feature of this topology is its ability to function in five-or three-level mode, in the entire modulation range, at full-power rating, in the event of any failure in the H-bridges. This feature significantly improves the reliability of the proposed drive system. Each leg of the three-phase two-level inverters used in this topology switches only for a half cycle of the reference voltage waveform. Hence, the effective switching frequency is reduced by half, resulting in switching loss reduction in high-voltage devices. The transient as well as the steady-state performance of the proposed nine-level inverter-fed IM drive system is experimentally verified in the entire modulation range including the overmodulation region.

Medium-Voltage Drive for Induction Machine With Multilevel Dodecagonal Voltage Space Vectors With Symmetric Triangles

Multilevel inverters with dodecagonal (12-sided polygon) voltage space vector structure have advantages, such as complete elimination of fifth and seventh harmonics, reduction in electromagnetic interference, reduction in device voltage ratings, reduction of switching frequency, extension of linear modulation range, etc., making it a viable option for high-power medium-voltage drives. This paper proposes two power circuit topologies capable of generating multilevel dodecagonal voltage space vector structure with symmetric triangles (for the first time) with minimum number of dc-link power supplies and floating capacitor H-bridges. The first power topology is composed of two hybrid cascaded five-level inverters connected to either side of an open-end winding induction machine. Each inverter consists of a three-level neutral-point-clamped inverter, which is cascaded with an isolated H-bridge making it a five-level inverter. The second topology is for a normal induction motor. Both of these circuit topologies have inherent capacitor balancing for floating H-bridges for all modulation indexes, including transient operations. The proposed topologies do not require any precharging circuitry for startup. A simple pulsewidth modulation timing calculation method for space vector modulation is also presented in this paper. Due to the symmetric arrangement of congruent triangles within the voltage space vector structure, the timing computation requires only the sampled reference values and does not require any offline computation, lookup tables, or angle computation. Experimental results for steady-state operation and transient operation are also presented to validate the proposed concept.

Energy Efficient Memory Decoder Design for Ultra-Low Voltage Systems

This paper presents a low energy memory decoder architecture for ultra-low-voltage systems containing multiple voltage domains. Due to limitations in scalability of memory supply voltages, these systems typically contain a core operating at subthreshold voltages and memories operating at a higher voltage. This difference in voltage provides a timing slack on the memory path as the core supply is scaled. The paper analyzes the feasibility and trade-offs in utilizing this timing slack to operate a greater section of memory decoder circuitry at the lower supply. A 256x16-bit SRAM interface has been designed in UMC 65nm low-leakage process to evaluate the above technique with the core and memory operating at 280 mV and 500 mV respectively. The technique provides a reduction of up to 20% in energy/cycle of the row decoder without any penalty in area and system-delay.