Formal verification and testing of software architectural models

Ensuring the correctness of software has been the major motivation in software research, constituting a Grand Challenge. Due to its impact in the final implementation, one critical aspect of software is its architectural design. By guaranteeing a correct architectural design, major and costly flaws can be caught early on in the development cycle. Software architecture design has received a lot of attention in the past years, with several methods, techniques and tools developed. However, there is still more to be done, such as providing adequate formal analysis of software architectures. On these regards, a framework to ensure system dependability from design to implementation has been developed at FIU (Florida International University). This framework is based on SAM (Software Architecture Model), an ADL (Architecture Description Language), that allows hierarchical compositions of components and connectors, defines an architectural modeling language for the behavior of components and connectors, and provides a specification language for the behavioral properties. The behavioral model of a SAM model is expressed in the form of Petri nets and the properties in first order linear temporal logic.^ This dissertation presents a formal verification and testing approach to guarantee the correctness of Software Architectures. The Software Architectures studied are expressed in SAM. For the formal verification approach, the technique applied was model checking and the model checker of choice was Spin. As part of the approach, a SAM model is formally translated to a model in the input language of Spin and verified for its correctness with respect to temporal properties. In terms of testing, a testing approach for SAM architectures was defined which includes the evaluation of test cases based on Petri net testing theory to be used in the testing process at the design level. Additionally, the information at the design level is used to derive test cases for the implementation level. Finally, a modeling and analysis tool (SAM tool) was implemented to help support the design and analysis of SAM models. The results show the applicability of the approach to testing and verification of SAM models with the aid of the SAM tool.^

Formal verification and testing of software architectural models

Ensuring the correctness of software has been the major motivation in software research, constituting a Grand Challenge. Due to its impact in the final implementation, one critical aspect of software is its architectural design. By guaranteeing a correct architectural design, major and costly flaws can be caught early on in the development cycle. Software architecture design has received a lot of attention in the past years, with several methods, techniques and tools developed. However, there is still more to be done, such as providing adequate formal analysis of software architectures. On these regards, a framework to ensure system dependability from design to implementation has been developed at FIU (Florida International University). This framework is based on SAM (Software Architecture Model), an ADL (Architecture Description Language), that allows hierarchical compositions of components and connectors, defines an architectural modeling language for the behavior of components and connectors, and provides a specification language for the behavioral properties. The behavioral model of a SAM model is expressed in the form of Petri nets and the properties in first order linear temporal logic. This dissertation presents a formal verification and testing approach to guarantee the correctness of Software Architectures. The Software Architectures studied are expressed in SAM. For the formal verification approach, the technique applied was model checking and the model checker of choice was Spin. As part of the approach, a SAM model is formally translated to a model in the input language of Spin and verified for its correctness with respect to temporal properties. In terms of testing, a testing approach for SAM architectures was defined which includes the evaluation of test cases based on Petri net testing theory to be used in the testing process at the design level. Additionally, the information at the design level is used to derive test cases for the implementation level. Finally, a modeling and analysis tool (SAM tool) was implemented to help support the design and analysis of SAM models. The results show the applicability of the approach to testing and verification of SAM models with the aid of the SAM tool.

Software Components for Serious Game Development

The large upfront investments required for game development pose a severe barrier for the wider uptake of serious games in education and training. Also, there is a lack of well-established methods and tools that support game developers at preserving and enhancing the games’ pedagogical effectiveness. The RAGE project, which is a Horizon 2020 funded research project on serious games, addresses these issues by making available reusable software components that aim to support the pedagogical qualities of serious games. In order to easily deploy and integrate these game components in a multitude of game engines, platforms and programming languages, RAGE has developed and validated a hybrid component-based software architecture that preserves component portability and interoperability. While a first set of software components is being developed, this paper presents selected examples to explain the overall system’s concept and its practical benefits. First, the Emotion Detection component uses the learners’ webcams for capturing their emotional states from facial expressions. Second, the Performance Statistics component is an add-on for learning analytics data processing, which allows instructors to track and inspect learners’ progress without bothering about the required statistics computations. Third, a set of language processing components accommodate the analysis of textual inputs of learners, facilitating comprehension assessment and prediction. Fourth, the Shared Data Storage component provides a technical solution for data storage - e.g. for player data or game world data - across multiple software components. The presented components are exemplary for the anticipated RAGE library, which will include up to forty reusable software components for serious gaming, addressing diverse pedagogical dimensions.

Uma arquitetura distribuída de hardware e software para controle de um robô móvel autônomo

BRITTO, Ricardo S.; MEDEIROS, Adelardo A. D.; ALSINA, Pablo J. Uma arquitetura distribuída de hardware e software para controle de um robô móvel autônomo. In: SIMPÓSIO BRASILEIRO DE AUTOMAÇÃO INTELIGENTE,8., 2007, Florianópolis. Anais... Florianópolis: SBAI, 2007.

Uma arquitetura distribuída de hardware e software para controle de um robô móvel autônomo

BRITTO, Ricardo S.; MEDEIROS, Adelardo A. D.; ALSINA, Pablo J. Uma arquitetura distribuída de hardware e software para controle de um robô móvel autônomo. In: SIMPÓSIO BRASILEIRO DE AUTOMAÇÃO INTELIGENTE,8., 2007, Florianópolis. Anais... Florianópolis: SBAI, 2007.

Phobos: The design and implementation of embedded software for a low cost radar warning receiver

This portfolio thesis describes work undertaken by the author under the Engineering Doctorate program of the Institute for System Level Integration. It was carried out in conjunction with the sponsor company Teledyne Defence Limited. A radar warning receiver is a device used to detect and identify the emissions of radars. They were originally developed during the Second World War and are found today on a variety of military platforms as part of the platform’s defensive systems. Teledyne Defence has designed and built components and electronic subsystems for the defence industry since the 1970s. This thesis documents part of the work carried out to create Phobos, Teledyne Defence’s first complete radar warning receiver. Phobos was designed to be the first low cost radar warning receiver. This was made possible by the reuse of existing Teledyne Defence products, commercial off the shelf hardware and advanced UK government algorithms. The challenges of this integration are described and discussed, with detail given of the software architecture and the development of the embedded application. Performance of the embedded system as a whole is described and qualified within the context of a low cost system.

Explorando a combinação de visualização de software com clusterização de dados em um processo de reconstrução de arquitetura

Dissertação (mestrado)—Universidade de Brasília, Instituto de Ciências Exatas, Departamento de Ciência da Computação, 2015.

GUI Behavior from Source Code Analysis

When developing interactive applications, considering the correctness of graphical user interfaces (GUIs) code is essential. GUIs are critical components of today's software, and contemporary software tools do not provide enough support for ensuring GUIs' code quality. GUIsurfer, a GUI reverse engineering tool, enables evaluation of behavioral properties of user interfaces. It performs static analysis of GUI code, generating state machines that can help in the evaluation of interactive applications. This paper describes the design, software architecture, and the use of GUIsurfer through an example. The tool is easily re-targetable, and support is available to Java/Swing, and WxHaskell. The paper sets the ground for a generalization effort to consider rich internet applications. It explores the GWT web applications' user interface programming toolkit.

Architectural prototyping: from CCS to .Net

Over the last decade, software architecture emerged as a critical issue in Software Engineering. This encompassed a shift from traditional programming towards software development based on the deployment and assembly of independent components. The specification of both the overall systems structure and the interaction patterns between their components became a major concern for the working developer. Although a number of formalisms to express behaviour and to supply the indispensable calculational power to reason about designs, are available, the task of deriving architectural designs on top of popular component platforms has remained largely informal. This paper introduces a systematic approach to derive, from CCS behavioural specifications the corresponding architectural skeletons in the Microsoft .Net framework, in the form of executable C and Cω code. The prototyping process is fully supported by a specific tool developed in Haskell

Prototyping Concurrent Systems in Cw

Software architecture is currently recognized as one of the most critical design steps in Software Engineering. The specification of the overall system structure, on the one hand, and of the interactions patterns between its components, on the other, became a major concern for the working developer. Although a number of formalisms to express behaviour and supply the indispensable calculational power to reason about designs, are available, the task of deriving architectural designs on top of popular component platforms has remained largely informal. This paper introduces a systematic approach to derive, from behavioural specifications written in Cw, the corresponding architectural skeletons in the Microsoft .NET framework in the form of executable code

Prototyping Behavioural Specifications in the.NET framework

Over the last decade, software architecture emerged as a critical design step in Software Engineering. This encompassed a shift from traditional programming towards the deployment and assembly of independent components. The specification of the overall system structure, on the one hand, and of the interactions patterns between its components, on the other, became a major concern for the working developer. Although a number of formalisms to express behaviour and supply the indispensable calculational power to reason about designs, are available, the task of deriving architectural designs on top of popular component platforms has remained largely informal. This paper introduces a systematic approach to derive, from behavioural specifications written in Ccs, the corresponding architectural skeletons in the Microsoft .Net framework in the form of executable C] code. Such prototyping process is automated by means of a specific tool developed in Haskell

Controlador Boundary-Scan

A crescente complexidade dos sistemas electrónicos associada a um desenvolvimento nas tecnologias de encapsulamento levou à miniaturização dos circuitos integrados, provocando dificuldades e limitações no diagnóstico e detecção de falhas, diminuindo drasticamente a aplicabilidade dos equipamentos ICT. Como forma de lidar com este problema surgiu a infra-estrutura Boundary Scan descrita na norma IEEE1149.1 “Test Access Port and Boundary-Scan Architecture”, aprovada em 1990. Sendo esta solução tecnicamente viável e interessante economicamente para o diagnóstico de defeitos, efectua também outras aplicações. O SVF surgiu do desejo de incutir e fazer com que os fornecedores independentes incluíssem a norma IEEE 1149.1, é desenvolvido num formato ASCII, com o objectivo de enviar sinais, aguardar pela sua resposta, segundo a máscara de dados baseada na norma IEEE1149.1. Actualmente a incorporação do Boundary Scan nos circuitos integrados está em grande expansão e consequentemente usufrui de uma forte implementação no mercado. Neste contexto o objectivo da dissertação é o desenvolvimento de um controlador boundary scan que implemente uma interface com o PC e possibilite o controlo e monitorização da aplicação de teste ao PCB. A arquitectura do controlador desenvolvido contém um módulo de Memória de entrada, um Controlador TAP e uma Memória de saída. A implementação do controlador foi feita através da utilização de uma FPGA, é um dispositivo lógico reconfiguráveis constituído por blocos lógicos e por uma rede de interligações, ambos configuráveis, que permitem ao utilizador implementar as mais variadas funções digitais. A utilização de uma FPGA tem a vantagem de permitir a versatilidade do controlador, facilidade na alteração do seu código e possibilidade de inserir mais controladores dentro da FPGA. Foi desenvolvido o protocolo de comunicação e sincronização entre os vários módulos, permitindo o controlo e monitorização dos estímulos enviados e recebidos ao PCB, executados automaticamente através do software do Controlador TAP e de acordo com a norma IEEE 1149.1. A solução proposta foi validada por simulação utilizando o simulador da Xilinx. Foram analisados todos os sinais que constituem o controlador e verificado o correcto funcionamento de todos os seus módulos. Esta solução executa todas as sequências pretendidas e necessárias (envio de estímulos) à realização dos testes ao PCB. Recebe e armazena os dados obtidos, enviando-os posteriormente para a memória de saída. A execução do trabalho permitiu concluir que os projectos de componentes electrónicos tenderão a ser descritos num nível de abstracção mais elevado, recorrendo cada vez mais ao uso de linguagens de hardware, no qual o VHDL é uma excelente ferramenta de programação. O controlador desenvolvido será uma ferramenta bastante útil e versátil para o teste de PCBs e outras funcionalidades disponibilizadas pelas infra-estruturas BS.

A smart layer for remote laboratories

Commonly, when a weblab is developed to support remote experiments in sciences and engineering courses, a particular hardware/software architecture is implemented. However, the existence of several technological solutions to implement those architectures difficults the emergence of a standard, both at hardware and software levels. While particular solutions are adopted assuming that only qualified people may implement a weblab, the control of the physical space and the power consumption are often forgotten. Since controlling these two previous aspects may increase the quality of the weblab hosting the remote experiments, this paper proposes the useof a new layer implemented by a domotic system bus with several devices (e.g. lights, power sockets, temperature sensors, and others) able to be controlled through the Internet. We also provide a brief proof-of-concept in the form of a weblab equipped with a simple domotic system usually implemented in smart houses. The added value to the remote experiment hosted at the weblab is also identified in terms of power savings and environment conditions.

A Web-Based geographical information system prototype on Portuguese traditional food products

Dissertation submitted in partial fulfilment of the requirements for the Degree of Master of Science in Geospatial Technologies

Pulseira inteligente para aplicações industriais e de lazer

Nos últimos anos, o avanço da tecnologia e a miniaturização de diversos componentes têm permitido o aparecimento de novos conceitos, ideias e projetos, que até aqui não passariam de filmes de ficção científica. Com a tecnologia atual, podem ser desenvolvidos pequenos dispositivos wearable com diversas interfaces, múltiplas conectividades, poder de processamento e autonomia. Permitindo desta forma, dar resposta à crescente necessidade de interação com os mais diversos equipamentos eletrónicos do dia-a-dia, melhorando o acesso e o fornecimento de informação. O principal objetivo deste trabalho passa assim por demonstrar e implementar um conceito que permita estreitar e facilitar a interação entre o utilizador e o mundo que o rodeia, quer em ambientes domésticos quer industriais. Para isso foi projetado e implementado um dispositivo wearable (para utilização no pulso) baseado numa arquitetura de hardware e software capaz de correr diferentes aplicações, tais como extensão de alertas de um smartphone, crowdsourcing de informações meteorológicas, manutenção e inspeção industrial e monitorização remota de forças de segurança. Os resultados obtidos demonstram que este conceito é viável tanto do ponto de vista técnico como funcional, evidenciando boas hipóteses para que estes conceitos, métodos e tecnologias possam ser integradas em plataformas robóticas desenvolvidas no âmbito de projetos do Laboratório de Sistemas Autónomos (LSA) bem como nos contextos industrial e de lazer.