Building object-oriented software with the D-Bus messaging system

Object-oriented programming is a widely adopted paradigm for desktop software development. This paradigm partitions software into separate entities, objects, which consist of data and related procedures used to modify and inspect it. The paradigm has evolved during the last few decades to emphasize decoupling between object implementations, via means such as explicit interface inheritance and event-based implicit invocation. Inter-process communication (IPC) technologies allow applications to interact with each other. This enables making software distributed across multiple processes, resulting in a modular architecture with benefits in resource sharing, robustness, code reuse and security. The support for object-oriented programming concepts varies between IPC systems. This thesis is focused on the D-Bus system, which has recently gained a lot of users, but is still scantily researched. D-Bus has support for asynchronous remote procedure calls with return values and a content-based publish/subscribe event delivery mechanism. In this thesis, several patterns for method invocation in D-Bus and similar systems are compared. The patterns that simulate synchronous local calls are shown to be dangerous. Later, we present a state-caching proxy construct, which avoids the complexity of properly asynchronous calls for object inspection. The proxy and certain supplementary constructs are presented conceptually as generic object-oriented design patterns. The e ect of these patterns on non-functional qualities of software, such as complexity, performance and power consumption, is reasoned about based on the properties of the D-Bus system. The use of the patterns reduces complexity, but maintains the other qualities at a good level. Finally, we present currently existing means of specifying D-Bus object interfaces for the purposes of code and documentation generation. The interface description language used by the Telepathy modular IM/VoIP framework is found to be an useful extension of the basic D-Bus introspection format.

Readout Electronics for Gas Electron Multiplier Detectors

The European Organization for Nuclear Research (CERN) operates the largest particle collider in the world. This particle collider is called the Large Hadron Collider (LHC) and it will undergo a maintenance break sometime in 2017 or 2018. During the break, the particle detectors, which operate around the particle collider, will be serviced and upgraded. Following the improvement in performance of the particle collider, the requirements for the detector electronics will be more demanding. In particular, the high amount of radiation during the operation of the particle collider sets requirements for the electronics that are uncommon in commercial electronics. Electronics that are built to function in the challenging environment of the collider have been designed at CERN. In order to meet the future challenges of data transmission, a GigaBit Transceiver data transmission module and an E-Link data bus have been developed. The next generation of readout electronics is designed to benefit from these technologies. However, the current readout electronics chips are not compatible with these technologies. As a result, in addition to new Gas Electron Multiplier (GEM) detectors and other technology, a new compatible chip is developed to function within the GEMs for the Compact Muon Solenoid (CMS) project. In this thesis, the objective was to study a data transmission interface that will be located on the readout chip between the E-Link bus and the control logic of the chip. The function of the module is to handle data transmission between the chip and the E-Link. In the study, a model of the interface was implemented with the Verilog hardware description language. This process was simulated by using chip design software by Cadence. State machines and operating principles with alternative possibilities for implementation are introduced in the E-Link interface design procedure. The functionality of the designed logic is demonstrated in simulation results, in which the implemented model is proven to be suitable for its task. Finally, suggestions that should be considered for improving the design have been presented.

Agent-based management systems for many-core platforms : rigorous design and efficient implementation

Due to various advantages such as flexibility, scalability and updatability, software intensive systems are increasingly embedded in everyday life. The constantly growing number of functions executed by these systems requires a high level of performance from the underlying platform. The main approach to incrementing performance has been the increase of operating frequency of a chip. However, this has led to the problem of power dissipation, which has shifted the focus of research to parallel and distributed computing. Parallel many-core platforms can provide the required level of computational power along with low power consumption. On the one hand, this enables parallel execution of highly intensive applications. With their computational power, these platforms are likely to be used in various application domains: from home use electronics (e.g., video processing) to complex critical control systems. On the other hand, the utilization of the resources has to be efficient in terms of performance and power consumption. However, the high level of on-chip integration results in the increase of the probability of various faults and creation of hotspots leading to thermal problems. Additionally, radiation, which is frequent in space but becomes an issue also at the ground level, can cause transient faults. This can eventually induce a faulty execution of applications. Therefore, it is crucial to develop methods that enable efficient as well as resilient execution of applications. The main objective of the thesis is to propose an approach to design agentbased systems for many-core platforms in a rigorous manner. When designing such a system, we explore and integrate various dynamic reconfiguration mechanisms into agents functionality. The use of these mechanisms enhances resilience of the underlying platform whilst maintaining performance at an acceptable level. The design of the system proceeds according to a formal refinement approach which allows us to ensure correct behaviour of the system with respect to postulated properties. To enable analysis of the proposed system in terms of area overhead as well as performance, we explore an approach, where the developed rigorous models are transformed into a high-level implementation language. Specifically, we investigate methods for deriving fault-free implementations from these models into, e.g., a hardware description language, namely VHDL.

Abstract platforms of computation

Computational formalisms have been pushing the boundaries of the field of computing for the last 80 years and much debate has surrounded what computing entails; what it is, and what it is not. This paper seeks to explore the boundaries of the ideas of computation and provide a framework for enabling a constructive discussion of computational ideas. First, a review of computing is given, ranging from Turing Machines to interactive computing. Then, a variety of natural physical systems are considered for their computational qualities. From this exploration, a framework is presented under which all dynamical systems can be considered as instances of the class of abstract computational platforms. An abstract computational platform is defined by both its intrinsic dynamics and how it allows computation that is meaningful to an external agent through the configuration of constraints upon those dynamics. It is asserted that a platform’s computational expressiveness is directly related to the freedom with which constraints can be placed. Finally, the requirements for a formal constraint description language are considered and it is proposed that Abstract State Machines may provide a reasonable basis for such a language.

Uma proposta de arquitetura de linha de produto para sistemas de gerenciamento de workflow

A tecnologia de workflow vem apresentando um grande crescimento nos últimos anos. Os Workflow Management Systems (WfMS) ou Sistemas de Gerenciamento de Workflow oferecem uma abordagem sistemática para uniformizar, automatizar e gerenciar os processos de negócios. Esta tecnologia requer técnicas de engenharia de software que facilitem a construção desse tipo de sistema. Há muito vem se formando uma consciência em engenharia de software de que para a obtenção de produtos com alta qualidade e que sejam economicamente viáveis torna-se necessário um conjunto sistemático de processos, técnicas e ferramentas. A reutilização está entre as técnicas mais relevantes desse conjunto. Parte-se do princípio que, reutilizando partes bem especificadas, desenvolvidas e testadas, pode-se construir software em menor tempo e com maior confiabilidade. Muitas técnicas que favorecem a reutilização têm sido propostas ao longo dos últimos anos. Entre estas técnicas estão: engenharia de domínio, frameworks, padrões, arquitetura de software e desenvolvimento baseado em componentes. Porém, o que falta nesse contexto é uma maneira sistemática e previsível de realizar a reutilização. Assim, o enfoque de linha de produto de software surge como uma proposta sistemática de desenvolvimento de software, baseada em uma família de produtos que compartilham um conjunto gerenciado de características entre seus principais artefatos. Estes artefatos incluem uma arquitetura base e um conjunto de componentes comuns para preencher esta arquitetura. O projeto de uma arquitetura para uma família de produtos deve considerar as semelhanças e variabilidades entre os produtos desta família. Esta dissertação apresenta uma proposta de arquitetura de linha de produto para sistemas de gerenciamento de workflow. Esta arquitetura pode ser usada para facilitar o processo de produção de diferentes sistemas de gerenciamento de workflow que possuem características comuns, mas que também possuam aspectos diferentes de acordo com as necessidades da indústria. O desenvolvimento da arquitetura proposta tomou como base a arquitetura genérica e o modelo de referência da Workflow Management Coalition (WfMC) e o padrão de arquitetura Process Manager desenvolvido no contexto do projeto ExPSEE1. O processo de desenvolvimento da arquitetura seguiu o processo sugerido pelo Catalysis com algumas modificações para representar variabilidade. A arquitetura proposta foi descrita e simulada através da ADL (Architecture Description Language) Rapide. A principal contribuição deste trabalho é uma arquitetura de linha de produto para sistemas de gerenciamento de workflow. Pode-se destacar também contribuições para uma proposta de sistematização de um processo de desenvolvimento de arquitetura de linha de produto e também um melhor entendimento dos conceitos e abordagens relacionados à prática de linha de produto, uma vez que esta tecnologia é recente e vem sendo largamente aplicada nas empresas.

T&D-bench : explorando o espaço de projeto de processadores em ensino e em pesquisa

Uma metodologia de modelagem para a exploração do espaço de projeto de processadores é apresentada. A exploração do espaço de projeto constitui uma das etapas do fluxo de projeto dos atuais processadores de alto desempenho e de sistemas embarcados, que auxilia os projetistas no tratamento da complexidade inerente ao processo contemporâneo de projeto de sistemas computacionais. A principal característica desta metodologia é um processo de modelagem simples e rápido. Isso é obtido através da disponibilização dos recursos de modelagem em camadas com propósitos e níveis de complexidade de uso diferenciados e da limitação do número de elementos (palavras-chave, classes e métodos) que devem ser conhecidos pelo projetista para o acesso a estes recursos, independentemente da camada na qual eles se encontram. A única exigência para o uso de tais recursos são conhecimentos que estudantes de Computação adquirem ao longo dos seus cursos da área de Computação e Informática. Outras características da metodologia de modelagem incluem: recursos específicos e distintos para a descrição da organização, da arquitetura e de aspectos temporais do processador; um estilo de descrição estrutural de alto nível da organização; a possibilidade de uso de recursos gráficos em tempo de modelagem e em tempo de simulação; e a existência de informações nos modelos que podem ser usadas para a tradução das descrições para uma Hardware Description Language Todas estas características constituem um conjunto de soluções de modelagem e simulação de processadores que não é encontrado em outros ambientes usados na exploração do espaço de projeto, baseados em Architecture Description Languages, Hardware Description Languages e ferramentas de simulação. Além disso, os modelos de processadores, desenvolvidos com esta metodologia, fornecem os recursos para a aceleração do aprendizado de conteúdos de arquitetura de computadores que só são encontrados em simuladores para ensino. Uma infra-estrutura de software que implementa a metodologia de modelagem foi desenvolvida e está disponível. Ela foi usada no ensino e no contexto da pesquisa para a modelagem e simulação de diversos processadores. Uma comparação com a metodologia de modelagem de uma Architecture Description Language demonstra a simplicidade e a rapidez do processo de modelagem previsto na metodologia apresentada.

Autoria e simulação de cenários de redes em NS-3

Este trabalho aborda a crescente necessidade de verificação e testes das redes antes da sua implementação no mundo real. Variáveis como o investimento, estudo qualidade-custo, questões de gestão, fiabilidade e tempo de vida útil são parte das principais preocupações associadas a existentes e futuras redes. É sobretudo neste âmbito que este projecto opera, fornecendo uma solução para uma optimização da autoria de cenários de redes visando a sua execução na ferramenta de simulação de redes NS-3. As tecnologias emergentes são os alvos mais comuns de ferramentas de simulação de redes e este facto é determinante ao decidir que simulador de redes usar para simular os seus cenários. Com este trabalho, o principal objectivo é fornecer aos utilizadores uma ferramenta colaborativa que permite descrever os seus próprios cenários de redes, baseando-se numa linguagem XML denominada por NSDL e traduzir esta estrutura XML para um script C++ que possa ser executado num ambiente evolucionário, como é o caso do NS-3. A solução proposta permite a rápida criação de cenários de redes através de estruturas de dados XML para posterior tradução para C++ e então, execução no NS-3. A maior problemática associada a esta solução é a necessidade de actualização constante em estruturas de validação e de tradução de documentos XML, aquando da actualização da ferramenta NS-3, o que tem vindo a acontecer muito frequentemente devido à sua própria evolução.

A New Approach for Real Time Fault Diagnosis in Induction Motors Based on Vibration Measurement

Condition monitoring is used to increase machinery availability and machinery performance, reducing consequential damage, increasing machine life, reducing spare parts inventories, and reducing breakdown maintenance. An efficient real time vibration measurement and analysis instruments is capable of providing warning and predicting faults at early stages. In this paper, a new methodology for the implementation of vibration measurement and analysis instruments in real time based on circuit architecture mapped from a MATLAB/Simulink model is presented. In this study, signal processing applications such as FIR filters and fast Fourier transform are treated as systems, which are implemented in hardware using a system generator toolbox, which translates a Simulink model in a hardware description language - HDL for FPGA implementations.

A 2kW interleaved ZCS-FM boost rectifier digitally controlled by FPGA device

This paper presents a 2kW single-phase high power factor boost rectifier with four cells in interleave connection, operating in critical conduction mode, and employing a soft-switching technique, controlled by Field Programmable Gate Array (FPGA). The soft-switching technique Is based on zero-current-switching (ZCS) cells, providing ZC (zero-current) turn-on and ZCZV (zero-current-zero-voltage) turn-off for the active switches, and ZV (zero-voltage) turn-on and ZC (zero-current) turn-off for the boost diodes. The disadvantages related 'to reverse recovery effects of boost diodes operated in continuous conduction mode (additional losses, and electromagnetic interference (EMI) problems) are minimized, due to the operation in critical conduction mode. In addition, due to the Interleaving technique, the rectifer's features include the reduction in the input current ripple, the reduction in the output voltage ripple, the use of low stress devices, low volume for the EMI input filter, high input power factor (PF), and low total harmonic distortion (THD) In the input current, in compliance with the TEC61000-3-2 standards. The digital controller has been developed using a hardware description language (VHDL) and implemented using a XC2S200E-SpartanII-E/Xilinx FPGA device, performing a true critical conduction operation mode for four interleaved cells, and a closed-loop to provide the output voltage regulation, like as a pre-regulator rectifier. Experimental results are presented for a 2kW implemented prototype with four interleaved cells, 400V nominal output voltage and 220V(rms) nominal input voltage, in order to verify the feasibility and performance of the proposed digital control through the use of a FPGA device.

DCM Boost interleaved converter for operation in AC and DC to trolleybus application

This paper is based on the development and experimental analysis of a DCM Boost interleaved converter suitable for application in traction systems of electrical vehicles pulled by electrical motors (Trolleybus), which are powered by urban DC or AC distribution networks. This front-end structure is capable of providing significant improvements in trolleybuses systems and in the urban distribution network costs, and efficiency. The architecture of proposed converter is composed by five boost power cells in interleaving connection, operating in discontinuous conduction mode. Furthermore, the converter can operate as AC-DC converter, or as DC-DC converter providing the proper DC output voltage range required by DC or AC adjustable speed drivers. Therefore, when supplied by single-phase AC distribution networks, and operating as AC-DC converter, it is capable to provide high power factor, reduced harmonic distortion in the input current, complying with the restrictions imposed by the IEC 61000-3-4 standards. The digital controller has been implemented using a low cost FPGA and developed totally using a hardware description language VHDL and fixed point arithmetic. Thus, two control strategies are evaluated considering the compliance with input current restrictions imposed by IEC 61000-3-4 standards, the regular PWM modulation and a current correction PWM modulation. In order to verify the feasibility and performance of the proposed system, experimental results from a 15 kW low power scale prototype are presented, operating in DC and AC conditions.

Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys

The increase of capacity to integrate transistors permitted to develop completed systems, with several components, in single chip, they are called SoC (System-on-Chip). However, the interconnection subsystem cans influence the scalability of SoCs, like buses, or can be an ad hoc solution, like bus hierarchy. Thus, the ideal interconnection subsystem to SoCs is the Network-on-Chip (NoC). The NoCs permit to use simultaneous point-to-point channels between components and they can be reused in other projects. However, the NoCs can raise the complexity of project, the area in chip and the dissipated power. Thus, it is necessary or to modify the way how to use them or to change the development paradigm. Thus, a system based on NoC is proposed, where the applications are described through packages and performed in each router between source and destination, without traditional processors. To perform applications, independent of number of instructions and of the NoC dimensions, it was developed the spiral complement algorithm, which finds other destination until all instructions has been performed. Therefore, the objective is to study the viability of development that system, denominated IPNoSys system. In this study, it was developed a tool in SystemC, using accurate cycle, to simulate the system that performs applications, which was implemented in a package description language, also developed to this study. Through the simulation tool, several result were obtained that could be used to evaluate the system performance. The methodology used to describe the application corresponds to transform the high level application in data-flow graph that become one or more packages. This methodology was used in three applications: a counter, DCT-2D and float add. The counter was used to evaluate a deadlock solution and to perform parallel application. The DCT was used to compare to STORM platform. Finally, the float add aimed to evaluate the efficiency of the software routine to perform a unimplemented hardware instruction. The results from simulation confirm the viability of development of IPNoSys system. They showed that is possible to perform application described in packages, sequentially or parallelly, without interruptions caused by deadlock, and also showed that the execution time of IPNoSys is more efficient than the STORM platform

Proposta e implementação de uma arquitetura reconfigurável híbrida para aplicações baseadas em fluxo de dados

The increase of applications complexity has demanded hardware even more flexible and able to achieve higher performance. Traditional hardware solutions have not been successful in providing these applications constraints. General purpose processors have inherent flexibility, since they perform several tasks, however, they can not reach high performance when compared to application-specific devices. Moreover, since application-specific devices perform only few tasks, they achieve high performance, although they have less flexibility. Reconfigurable architectures emerged as an alternative to traditional approaches and have become an area of rising interest over the last decades. The purpose of this new paradigm is to modify the device s behavior according to the application. Thus, it is possible to balance flexibility and performance and also to attend the applications constraints. This work presents the design and implementation of a coarse grained hybrid reconfigurable architecture to stream-based applications. The architecture, named RoSA, consists of a reconfigurable logic attached to a processor. Its goal is to exploit the instruction level parallelism from intensive data-flow applications to accelerate the application s execution on the reconfigurable logic. The instruction level parallelism extraction is done at compile time, thus, this work also presents an optimization phase to the RoSA architecture to be included in the GCC compiler. To design the architecture, this work also presents a methodology based on hardware reuse of datapaths, named RoSE. RoSE aims to visualize the reconfigurable units through reusability levels, which provides area saving and datapath simplification. The architecture presented was implemented in hardware description language (VHDL). It was validated through simulations and prototyping. To characterize performance analysis some benchmarks were used and they demonstrated a speedup of 11x on the execution of some applications

Uma ontologia para a descrição da semântica da IMML

This work presents an ontology to describe the semantics of IMML (Interactive Message Modeling Language) an XML-based User Interface Description Language. The ontology presents the description of all IMML elements including a natural language description and semantic rules and relationships. The ontology is implemented in OWL-DL, a standard language to ontology description that is recommended by W3C. Our main goal is to describe the semantic using languages and tools that can be processed by computers. As a consequence, we develop tools to the validation of a user interface specification and also to present the semantic description in different views

Um modelo conceitual baseado em MDD e padrões para evolução de sistemas OA

Aspect-Oriented Software Development (AOSD) is a technique that complements the Object- Oriented Software Development (OOSD) modularizing several concepts that OOSD approaches do not modularize appropriately. However, the current state-of-the art on AOSD suffers with software evolution, mainly because aspect definition can stop to work correctly when base elements evolve. A promising approach to deal with that problem is the definition of model-based pointcuts, where pointcuts are defined based on a conceptual model. That strategy makes pointcut less prone to software evolution than model-base elements. Based on that strategy, this work defines a conceptual model at high abstraction level where we can specify software patterns and architectures that through Model Driven Development techniques they can be instantiated and composed in architecture description language that allows aspect modeling at architecture level. Our MDD approach allows propagate concepts in architecture level to another abstraction levels (design level, for example) through MDA transformation rules. Also, this work shows a plug-in implemented to Eclipse platform called AOADLwithCM. That plug-in was created to support our development process. The AOADLwithCM plug-in was used to describe a case study based on MobileMedia System. MobileMedia case study shows step-by-step how the Conceptual Model approach could minimize Pointcut Fragile Problems, due to software evolution. MobileMedia case study was used as input to analyses evolutions on software according to software metrics proposed by KHATCHADOURIAN, GREENWOOD and RASHID. Also, we analyze how evolution in base model could affect maintenance on aspectual model with and without Conceptual Model approaches

Geração automática de hardware a partir de especificações formais: estendendo uma abordagem de tradução

Removing inconsistencies in a project is a less expensive activity when done in the early steps of design. The use of formal methods improves the understanding of systems. They have various techniques such as formal specification and verification to identify these problems in the initial stages of a project. However, the transformation from a formal specification into a programming language is a non-trivial task and error prone, specially when done manually. The aid of tools at this stage can bring great benefits to the final product to be developed. This paper proposes the extension of a tool whose focus is the automatic translation of specifications written in CSPM into Handel-C. CSP is a formal description language suitable for concurrent systems, and CSPM is the notation used in tools support. Handel-C is a programming language whose result can be compiled directly into FPGA s. Our extension increases the number of CSPM operators accepted by the tool, allowing the user to define local processes, to rename channels in a process and to use Boolean guards on external choices. In addition, we also propose the implementation of a communication protocol that eliminates some restrictions on parallel composition of processes in the translation into Handel-C, allowing communication in a same channel between multiple processes to be mapped in a consistent manner and that improper communication in a channel does not ocurr in the generated code, ie, communications that are not allowed in the system specification