Semi-analytic slope delay model for CMOS switch-level timing verification

A novel slope delay model for CMOS switch-level timing verification is presented. It differs from conventional methods in being semianalytic in character. The model assumes that all input waveforms are trapezoidal in overall shape, but that they vary in their slope. This simplification is quite reasonable and does not seriously affect precision, but it facilitates rapid solution. The model divides the stages in a switch-level circuit into two types. One corresponds to the logic gates, and the other corresponds to logic gates with pass transistors connected to their outputs. Semianalytic modeling for both cases is discussed.

Switch-level timing verification for CMOS circuits. A semianalytic approach

The paper describes a semianalytic slope delay model for CMOS switch-level timing verification. It is characterised by classification of the effects of the input slope, internal size and load capacitance of a logic gate on delay time, and then the use of a series of carefully chosen analytic functions to estimate delay times under different circumstances. In the field of VLSI analysis, this model achieves improvements in speed and accuracy compared with conventional approaches to transistor-level and switch-level simulation.

Free-Space Interconnect for Optical Switch and Analogue Neural Network

In this paper, the architecture of a vector-matrix multiplier (MVM) is simulated. The optical design can be made compact by the use of GRIN lenses for the optical fan-in. The intended application area was in storage area networks (SANs) but the concept can be applied to a neural network. © 2011 Allerton Press, Inc.

Pull-In Instability Of Micro-Switch Actuators: Model Review

The existing three widely used pull-in theoretical models (i.e., one-dimensional lumped model, linear supposition model and planar model) are compared with the nonlinear beam mode in this paper by considering both cantilever and fixed-fixed type micro and nano-switches. It is found that the error of the pull-in parameters between one-dimensional lumped model and the nonlinear beam model is large because the denominator of the electrostatic force is minimal when the electrostatic force is computed at the maximum deflection along the beam. Since both the linear superposition model and the slender planar model consider the variation of electrostatic force with the beam's deflection, these two models not only are of the same type but also own little error of the pull-in parameters with the nonlinear beam model, the error brought by these two models attributes to that the boundary conditions are not completely satisfied when computing the numerical integration of the deflection.