MSGR-based Low Latency Complex Matrix Inversion Architecture

This paper presents a matrix inversion architecture based on the novel Modified Squared Givens Rotations (MSGR) algorithm, which extends the original SGR method to complex valued data, and also corrects erroneous results in the original SGR method when zeros occur on the diagonal of the matrix either initially or during processing. The MSGR algorithm also avoids complex dividers in the matrix inversion, thus minimising the complexity of potential real-time implementations. A systolic array architecture is implemented and FPGA synthesis results indicate a high-throughput low-latency complex matrix inversion solution. © 2008 IEEE.

Generic low-latency NoC router architecture for FPGA computing systems

A novel cost-effective and low-latency wormhole router for packet-switched NoC designs, tailored for FPGA, is presented. This has been designed to be scalable at system level to fully exploit the characteristics and constraints of FPGA based systems, rather than custom ASIC technology. A key feature is that it achieves a low packet propagation latency of only two cycles per hop including both router pipeline delay and link traversal delay - a significant enhancement over existing FPGA designs - whilst being very competitive in terms of performance and hardware complexity. It can also be configured in various network topologies including 1-D, 2-D, and 3-D. Detailed design-space exploration has been carried for a range of scaling parameters, with the results of various design trade-offs being presented and discussed. By taking advantage of abundant buildin reconfigurable logic and routing resources, we have been able to create a new scalable on-chip FPGA based router that exhibits high dimensionality and connectivity. The architecture proposed can be easily migrated across many FPGA families to provide flexible, robust and cost-effective NoC solutions suitable for the implementation of high-performance FPGA computing systems. © 2011 IEEE.

Rigorous Specification and Low-Latency Implementation of Technical Market Indicators

Technical market indicators are tools used by technical an- alysts to understand trends in trading markets. Technical (market) indicators are often calculated in real-time, as trading progresses. This paper presents a mathematically- founded framework for calculating technical indicators. Our framework consists of a domain specific language for the un- ambiguous specification of technical indicators, and a run- time system based on Click, for computing the indicators. We argue that our solution enhances the ease of program- ming due to aligning our domain-specific language to the mathematical description of technical indicators, and that it enables executing programs in kernel space for decreased latency, without exposing the system to users’ programming errors.

Strength of visual percept generated by famous faces perceived without awareness: effects of affective valence, response latency, and visual field

Participants who were unable to detect familiarity from masked 17 ms faces ([Stone and Valentine, 2004] and [Stone and Valentine, in press-b]) did report a vague, partial visual percept. Two experiments investigated the relative strength of the visual percept generated by famous and unfamiliar faces, using masked 17 ms exposure. Each trial presented simultaneously a famous and an unfamiliar face, one face in LVF and the other in RVF. In one task, participants responded according to which of the faces generated the stronger visual percept, and in the other task, they attempted an explicit familiarity decision. The relative strength of the visual percept of the famous face compared to the unfamiliar face was moderated by response latency and participants’ attitude towards the famous person. There was also an interaction of visual field with response latency, suggesting that the right hemisphere can generate a visual percept differentiating famous from unfamiliar faces more rapidly than the left hemisphere. Participants were at chance in the explicit familiarity decision, confirming the absence of awareness of facial familiarity.

Dynamics of HIV latency and reactivation in a primary CD4+ T cell model.

HIV latency is a major obstacle to curing infection. Current strategies to eradicate HIV aim at increasing transcription of the latent provirus. In the present study we observed that latently infected CD4+ T cells from HIV-infected individuals failed to produce viral particles upon ex vivo exposure to SAHA (vorinostat), despite effective inhibition of histone deacetylases. To identify steps that were not susceptible to the action of SAHA or other latency reverting agents, we used a primary CD4+ T cell model, joint host and viral RNA sequencing, and a viral-encoded reporter. This model served to investigate the characteristics of latently infected cells, the dynamics of HIV latency, and the process of reactivation induced by various stimuli. During latency, we observed persistence of viral transcripts but only limited viral translation. Similarly, the reactivating agents SAHA and disulfiram successfully increased viral transcription, but failed to effectively enhance viral translation, mirroring the ex vivo data. This study highlights the importance of post-transcriptional blocks as one mechanism leading to HIV latency that needs to be relieved in order to purge the viral reservoir.

Subjective, behavioural and electrophysiological measurements of the time-course and intensity of sleep inertia after a full night of sleep /

Several recent studies have described the period of impaired alertness and performance known as sleep inertia that occurs upon awakening from a full night of sleep. They report that sleep inertia dissipates in a saturating exponential manner, the exact time course being task dependent, but generally persisting for one to two hours. A number of factors, including sleep architecture, sleep depth and circadian variables are also thought to affect the duration and intensity. The present study sought to replicate their findings for subjective alertness and reaction time and also to examine electrophysiological changes through the use of event-related potentials (ERPs). Secondly, several sleep parameters were examined for potential effects on the initial intensity of sleep inertia. Ten participants spent two consecutive nights and subsequent mornings in the sleep lab. Sleep architecture was recorded for a fiiU nocturnal episode of sleep based on participants' habitual sleep patterns. Subjective alertness and performance was measured for a 90-minute period after awakening. Alertness was measured every five minutes using the Stanford Sleepiness Scale (SSS) and a visual analogue scale (VAS) of sleepiness. An auditory tone also served as the target stimulus for an oddball task designed to examine the NlOO and P300 components ofthe ERP waveform. The five-minute oddball task was presented at 15-minute intervals over the initial 90-minutes after awakening to obtain six measures of average RT and amplitude and latency for NlOO and P300. Standard polysomnographic recording were used to obtain digital EEG and describe the night of sleep. Power spectral analyses (FFT) were used to calculate slow wave activity (SWA) as a measure of sleep depth for the whole night, 90-minutes before awakening and five minutes before awakening.

High performance, low latency double digit decimal multiplier on ASIC and FPGA

Decimal multiplication is an integral part of financial, commercial, and internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that offers low latency and high throughput. This design performs two digit multiplications simultaneously in one clock cycle. Double digit fixed point decimal multipliers for 7digit, 16 digit and 34 digit are simulated using Leonardo Spectrum from Mentor Graphics Corporation using ASIC Library. The paper also presents area and delay comparisons for these fixed point multipliers on Xilinx, Altera, Actel and Quick logic FPGAs. This multiplier design can be extended to support decimal floating point multiplication for IEEE 754- 2008 standard.

Estudio del desarrollo evolutivo y una comparación con disléxicos a través del potencial P300 auditivo.

Estudiar el desarrollo evolutivo a través de la técnica de potenciales evocados. Estudiar las diferencias de los potenciales evocados auditivos en niños de intervalos distintos de edad. Extraer datos que permitan relacionar los potenciales evocados cognitivos con las etapas de maduración del sistema nervioso central en niños normales, que puedan emplearse en la evaluación y eventualmente, en intervención psicopedagógica. Hipotésis: que los sujetos normales tienen el potencial P300 audio con caracteres diferentes según evolucionan con la edad. Diferencias que se manifiestan en un progresivo aumento de la amplitud, progresiva disminución de la latencia, diferencias interhemisféricas dadas por la latencia y amplitud y en la forma y duración de dicho componente a medida que el individuo va desarrollándose físicamente. Se seleccionaron 57 alumnos de 500 examinados pertenecientes a los colegios públicos Carmen Conde y Virgen del Carmen de Cartagena (29 niños y 28 niñas). Los criterios para la selección fueron: informe del profesor sobre la capacidad y logros en el aprendizaje así como sobre sus relaciones afectivas y personales (se seleccionaron los que no presentaban dificultades). Consulta a las familias sobre posibles tratamientos neurológicos o farmacológicos (se seleccionaron los que no). Test Bender. Escala de inteligencia Wechsler (se seleccionaron los que ofrecían puntuaciones normales, igual o superiores a la media de su edad). La prueba de potenciales evocados se realizó en el hospital Virgen del Rossel de Cartagena, en el Servicio de Neurofisiología. El registro se llevó a cabo con el aparato NEUROPACK FOVR, mod. MEM-4104 (sistema de registro neural). Para el registro se utilizaron un total de 4 electrodos y el proceso general consistió en adquisición, amplificación, filtrado, promediado y tratamiento gráfico. Variable independiente: prueba de potenciales evocados auditivos, en la que se presentaba una situación estandar para la obtención del potencial P300. Variables dependientes: valores alcanzados en el potencial P300 analizando: latencia, amplitud, diferencias hemisféricas, forma y duración. Test Bender (Bender, L., 1979, Test guestáltico visomotor, Paidós). Escala de inteligencia Wechsler (Wechsler, D., 1974. Escala de inteligencia Wechsler para niños. TEA Ediciones). Los potenciales evocados (ERP) son una medida del procesamiento de la información en el sistema nervioso central que puede utilizarse para establecer una comparación entre la población normal y la población patológica. Estos pueden proporcionar documentación de los estados y utilización corticales en el procesamiento cognitivo que no pueden ser conocidos por medidas de conducta.

Latency and slope values of evoked responses in children in brain stem audiometry

This paper is a review of a study to compare latencies of early evoked responses in young children with those of adults.

Minimising the latency induced by consistency control, within a large scale multi-user distributed virtual reality system

Where users are interacting in a distributed virtual environment, the actions of each user must be observed by peers with sufficient consistency and within a limited delay so as not to be detrimental to the interaction. The consistency control issue may be split into three parts: update control; consistent enactment and evolution of events; and causal consistency. The delay in the presentation of events, termed latency, is primarily dependent on the network propagation delay and the consistency control algorithms. The latency induced by the consistency control algorithm, in particular causal ordering, is proportional to the number of participants. This paper describes how the effect of network delays may be reduced and introduces a scalable solution that provides sufficient consistency control while minimising its effect on latency. The principles described have been developed at Reading over the past five years. Similar principles are now emerging in the simulation community through the HLA standard. This paper attempts to validate the suggested principles within the schema of distributed simulation and virtual environments and to compare and contrast with those described by the HLA definition documents.