996 resultados para Metal-insulator-metal


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We have grown epitaxially orientation-controlled monoclinic VO2 nanowires without employing catalysts by a vapor-phase transport process. Electron microscopy results reveal that single crystalline VO2 nanowires having a [100] growth direction grow laterally on the basal c plane and out of the basal r and a planes of sapphire, exhibiting triangular and rectangular cross sections, respectively. In addition, we have directly observed the structural phase transition of single crystalline VO2 nanowires between the monoclinic and tetragonal phases which exhibit insulating and metallic properties, respectively, and clearly analyzed their corresponding relationships using in situ transmission electron microscopy.

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In the present work, an infrared light-emitting diode is used to photodope molecular-beam-epitaxy-grown Si: Al0.3Ga0.7As, a well-known persistent photoconductor, to vary the effective electron concentration of samples in situ. Using this technique, we examine the transport properties of two samples containing different nominal doping concentrations of Si [1 x 10(19) cm(-3) for sample 1 (S1) and 9 x 10(17) cm(-3) for sample 2 (S2)] and vary the effective electron density between 10(14) and 10(18) cm(-3). The metal-insulator transition for S1 is found to occur at a critical carrier concentration of 5.7 x 10(16) cm(-3) at 350 mK. The mobilities in both samples are found to be limited by ionized impurity scattering in the temperature range probed, and are adequately described by the Brooks-Herring screening theory for higher carrier densities. The shape of the band tail of the density of states in Al0.3Ga0.7As is found electrically through transport measurements. It is determined to have a power-law dependence, with an exponent of -1.25 for S1 and -1.38 for S2.

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The GaN film was grown on the (111) silicon-on-insulator (SOI) substrate by metal-organic chemical vapor deposition and then annealed in the deposition chamber. A multiple beam optical stress sensor was used for the in-situ stress measurement, and X-ray diffraction (XRD) and Raman spectroscopy were used for the characterization of GaN film. Comparing the characterization results of the GaN films on the bulk silicon and SOI substrates, we can see that the Raman spectra show the 3.0 cm(-1) frequency shift of E-2(TO), and the full width at half maximum of XRD rocking curves for GaN (0002) decrease from 954 arc see to 472 are sec. The results show that the SOI substrates can reduce the tensile stress in the GaN film and improve the crystalline quality. The annealing process is helpful for the stress reduction of the GaN film. The SOI substrate with the thin top silicon film is more effective than the thick top silicon film SOI substrate for the stress reduction. (C) 2007 Elsevier B.V. All rights reserved.

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GaN epilayers have been deposited on silicon-on-insulator (SOI) and bulk silicon substrates. The stress transition thickness and the initial compressive stress of a GaN epilayer on the SOI substrate are larger than those on the bulk silicon substrate, as shown in in situ stress measurement results. It is mainly due to the difference of the three-dimensional island density and the threading dislocation density in the GaN layer. It can increase the compressive stress in the initial stage of growth of the GaN layer, and helps to offset the tensile stress generated by the lattice mismatch.

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We investigated electrical properties of vanadyl phthalocyanine (VOPc) metal-insulator-semiconductor (MIS) devices by the measurement of capacitance and conductance, which were fabricated on ordered para-sexiphenyl (p-6P) layer by weak epitaxy growth method. The VOPc/p-6P MIS diodes showed a negligible hysteresis effect at a gate voltage of +/- 20 V and small hysteresis effect at a gate voltage of +/- 40 V due to the low interface trap state density of about 1x10(10) eV(-1) cm(-2). Furthermore, a high transition frequency of about 10 kHz was also observed under their accumulation mode. The results indicated that VOPc was a promising material and was suitable to be applied in active matrix liquid crystal displays and organic logic circuits.

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Here we consider the numerical optimization of active surface plasmon polariton (SPP) trench waveguides suited for integration with luminescent polymers for use as highly localized SPP source devices in short-scale communication integrated circuits. The numerical analysis of the SPP modes within trench waveguide systems provides detailed information on the mode field components, effective indices, propagation lengths and mode areas. Such trench waveguide systems offer extremely high confinement with propagation on length scales appropriate to local interconnects, along with high efficiency coupling of dipolar emitters to waveguided plasmonic modes which can be close to 80%. The large Purcell factor exhibited in these structures will further lead to faster modulation capabilities along with an increased quantum yield beneficial for the proposed plasmon-emitting diode, a plasmonic analog of the light-emitting diode. The confinement of studied guided modes is on the order of 50 nm and the delay over the shorter 5 μm length scales will be on the order of 0.1 ps for the slowest propagating modes of the system, and significantly less for the faster modes.

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A simple model is developed for the admittance of a metal-insulator-semiconductor (MIS) capacitor which includes the effect of a guard ring surrounding the Ohmic contact to the semiconductor. The model predicts most of the features observed in a MIS capacitor fabricated using regioregular poly(3-hexylthiophene) as the active semiconductor and polysilsesquioxane as the gate insulator. In particular, it shows that when the capacitor is driven into accumulation, the parasitic transistor formed by the guard ring and Ohmic contact can give rise to an additional feature in the admittance-voltage plot that could be mistaken for interface states. When this artifact and underlying losses in the bulk semiconductor are accounted for, the remaining experimental feature, a peak in the loss-voltage plot when the capacitor is in depletion, is identified as an interface (or near interface) state of density of similar to 4 x 10(10) cm(-2) eV(-1). Application of the model shows that exposure of a vacuum-annealed device to laboratory air produces a rapid change in the doping density in the channel region of the parasitic transistor but only slow changes in the bulk semiconductor covered by the gold Ohmic contact. (C) 2008 American Institute of Physics.

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Low frequency admittance measurements are used to determine the density of interface states in metal-insulator-semiconductor diodes based on the unintentionally doped, p-type semiconductor poly(3-hexylthiophene). After vacuum annealing at 90 degrees C, interface hole trapping states are shown to be distributed in energy with their density decreasing approximately linearly from similar to 20x10(10) to 5x10(10) cm(-2) eV(-1) over an energy range extending from 0.05 to 0.25 eV above the bulk Fermi level. (c) 2008 American Institute of Physics.

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Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

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Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

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Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)