Real-time fault injection using enhanced on-chip debug infrastructures

The rapid increase in the use of microprocessor-based systems in critical areas, where failures imply risks to human lives, to the environment or to expensive equipment, significantly increased the need for dependable systems, able to detect, tolerate and eventually correct faults. The verification and validation of such systems is frequently performed via fault injection, using various forms and techniques. However, as electronic devices get smaller and more complex, controllability and observability issues, and sometimes real time constraints, make it harder to apply most conventional fault injection techniques. This paper proposes a fault injection environment and a scalable methodology to assist the execution of real-time fault injection campaigns, providing enhanced performance and capabilities. Our proposed solutions are based on the use of common and customized on-chip debug (OCD) mechanisms, present in many modern electronic devices, with the main objective of enabling the insertion of faults in microprocessor memory elements with minimum delay and intrusiveness. Different configurations were implemented starting from basic Components Off-The-Shelf (COTS) microprocessors, equipped with real-time OCD infrastructures, to improved solutions based on modified interfaces, and dedicated OCD circuitry that enhance fault injection capabilities and performance. All methodologies and configurations were evaluated and compared concerning performance gain and silicon overhead.

Reliability and availability in reconfigurable computing: a basis for a common solution

Dynamically reconfigurable SRAM-based field-programmable gate arrays (FPGAs) enable the implementation of reconfigurable computing systems where several applications may be run simultaneously, sharing the available resources according to their own immediate functional requirements. To exclude malfunctioning due to faulty elements, the reliability of all FPGA resources must be guaranteed. Since resource allocation takes place asynchronously, an online structural test scheme is the only way of ensuring reliable system operation. On the other hand, this test scheme should not disturb the operation of the circuit, otherwise availability would be compromised. System performance is also influenced by the efficiency of the management strategies that must be able to dynamically allocate enough resources when requested by each application. As those resources are allocated and later released, many small free resource blocks are created, which are left unused due to performance and routing restrictions. To avoid wasting logic resources, the FPGA logic space must be defragmented regularly. This paper presents a non-intrusive active replication procedure that supports the proposed test methodology and the implementation of defragmentation strategies, assuring both the availability of resources and their perfect working condition, without disturbing system operation.

On-line self-healing of circuits implemented on reconfigurable FPGAs

To boost logic density and reduce per unit power consumption SRAM-based FPGAs manufacturers adopted nanometric technologies. However, this technology is highly vulnerable to radiation-induced faults, which affect values stored in memory cells, and to manufacturing imperfections. Fault tolerant implementations, based on Triple Modular Redundancy (TMR) infrastructures, help to keep the correct operation of the circuit. However, TMR is not sufficient to guarantee the safe operation of a circuit. Other issues like module placement, the effects of multi- bit upsets (MBU) or fault accumulation, have also to be addressed. In case of a fault occurrence the correct operation of the affected module must be restored and/or the current state of the circuit coherently re-established. A solution that enables the autonomous restoration of the functional definition of the affected module, avoiding fault accumulation, re-establishing the correct circuit state in real-time, while keeping the normal operation of the circuit, is presented in this paper.

A framework for self-healing radiation-tolerant implementations on reconfigurable FPGAs

To increase the amount of logic available in SRAM-based FPGAs manufacturers are using nanometric technologies to boost logic density and reduce prices. However, nanometric scales are highly vulnerable to radiation-induced faults that affect values stored in memory cells. Since the functional definition of FPGAs relies on memory cells, they become highly prone to this type of faults. Fault tolerant implementations, based on triple modular redundancy (TMR) infrastructures, help to keep the correct operation of the circuit. However, TMR is not sufficient to guarantee the safe operation of a circuit. Other issues like the effects of multi-bit upsets (MBU) or fault accumulation, have also to be addressed. Furthermore, in case of a fault occurrence the correct operation of the affected module must be restored and the current state of the circuit coherently re-established. A solution that enables the autonomous correct restoration of the functional definition of the affected module, avoiding fault accumulation, re-establishing the correct circuit state in realtime, while keeping the normal operation of the circuit, is presented in this paper.

A framework for fault tolerant real time systems based on reconfigurable FPGAs

To increase the amount of logic available to the users in SRAM-based FPGAs, manufacturers are using nanometric technologies to boost logic density and reduce costs, making its use more attractive. However, these technological improvements also make FPGAs particularly vulnerable to configuration memory bit-flips caused by power fluctuations, strong electromagnetic fields and radiation. This issue is particularly sensitive because of the increasing amount of configuration memory cells needed to define their functionality. A short survey of the most recent publications is presented to support the options assumed during the definition of a framework for implementing circuits immune to bit-flips induction mechanisms in memory cells, based on a customized redundant infrastructure and on a detection-and-fix controller.

A modified debugging infrastructure to assist real time fault injection campaigns

Fault injection is frequently used for the verification and validation of the fault tolerant features of microprocessors. This paper proposes the modification of a common on-chip debugging (OCD) infrastructure to add fault injection capabilities and improve performance. The proposed solution imposes a very low logic overhead and provides a flexible and efficient mechanism for the execution of fault injection campaigns, being applicable to different target system architectures.

Collaborative learning in a qeb-accessible workbench

Web-based course management and delivery is regarded by many institutions as a key factor in an increasingly competitive education and training world, but the systems currently available are largely unsatisfactory in terms of supporting collaborative work and access to practical science facilities. These limitations are less important in areas where “pen-and-paper” courseware is the mainstream, but become unacceptably restrictive when student assignments require real-time teamwork and access to laboratory equipment. This paper presents a web-accessible workbench for electronics design and test, which was developed in the scope of an European IST project entitled PEARL, with the aim of supporting two main features: full web access and collaborative learning facilities.

A self-healing real-time system based on run-time self-reconfiguration

The new generations of SRAM-based FPGA (field programmable gate array) devices are the preferred choice for the implementation of reconfigurable computing platforms intended to accelerate processing in real-time systems. However, FPGA's vulnerability to hard and soft errors is a major weakness to robust configurable system design. In this paper, a novel built-in self-healing (BISH) methodology, based on run-time self-reconfiguration, is proposed. A soft microprocessor core implemented in the FPGA is responsible for the management and execution of all the BISH procedures. Fault detection and diagnosis is followed by repairing actions, taking advantage of the dynamic reconfiguration features offered by new FPGA families. Meanwhile, modular redundancy assures that the system still works correctly

On-line defragmentation for run-time partially reconfigurable FPGAs

Dynamically reconfigurable systems have benefited from a new class of FPGAs recently introduced into the market, which allow partial and dynamic reconfiguration at run-time, enabling multiple independent functions from different applications to share the same device, swapping resources as needed. When the sequence of tasks to be performed is not predictable, resource allocation decisions have to be made on-line, fragmenting the FPGA logic space. A rearrangement may be necessary to get enough contiguous space to efficiently implement incoming functions, to avoid spreading their components and, as a result, degrading their performance. This paper presents a novel active replication mechanism for configurable logic blocks (CLBs), able to implement on-line rearrangements, defragmenting the available FPGA resources without disturbing those functions that are currently running.

A new approach to assess defragmentation strategies in dynamically reconfigurable FPGAs

Fragmentation on dynamically reconfigurable FPGAs is a major obstacle to the efficient management of the logic space in reconfigurable systems. When resource allocation decisions have to be made at run-time a rearrangement may be necessary to release enough contiguous resources to implement incoming functions. The feasibility of run-time relocation depends on the processing time required to set up rearrangements. Moreover, the performance of the relocated functions should not be affected by this process or otherwise the whole system performance, and even its operation, may be at risk. Relocation should take into account not only specific functional issues, but also the FPGA architecture, since these two aspects are normally intertwined. A simple and fast method to assess performance degradation of a function during relocation and to speed up the defragmentation process, based on previous function labelling and on the application of the Euclidian distance concept, is proposed in this paper.

Institutional factors governing the deployment of remote experiments: lessons from the rexnet project

Remote labs offer many unique advantages to students as they provide opportunities to access experiments and learning scenarios that would be otherwise unavailable. At the same time, however, these opportunities introduce real challenges to the institutions hosting the remote labs. This paper draws on the experiences of the REXNET project consortium to expose a number of these issues as a means of furthering the debate on the value of remote labs and the best practices in deploying them. The paper presents a brief outline of the various types of remote lab scenarios that might be deployed. It then describes the key human and technological actors that have an interest in or are intrinsic to a remote lab instance, with a description of the role of each actor and their interest. Some relationships between these various actors are then discussed with some factors that might influence those relationships. Finally some general issues are briefly described.

Run-time defragmentation for dynamically reconfigurable hardware

Reconfigurable computing experienced a considerable expansion in the last few years, due in part to the fast run-time partial reconfiguration features offered by recent SRAM-based Field Programmable Gate Arrays (FPGAs), which allowed the implementation in real-time of dynamic resource allocation strategies, with multiple independent functions from different applications sharing the same logic resources in the space and temporal domains. However, when the sequence of reconfigurations to be performed is not predictable, the efficient management of the logic space available becomes the greatest challenge posed to these systems. Resource allocation decisions have to be made concurrently with system operation, taking into account function priorities and optimizing the space currently available. As a consequence of the unpredictability of this allocation procedure, the logic space becomes fragmented, with many small areas of free resources failing to satisfy most requests and so remaining unused. A rearrangement of the currently running functions is therefore necessary, so as to obtain enough contiguous space to implement incoming functions, avoiding the spreading of their components and the resulting degradation of system performance. A novel active relocation procedure for Configurable Logic Blocks (CLBs) is herein presented, able to carry out online rearrangements, defragmenting the available FPGA resources without disturbing functions currently running.

Forças em estruturas de acostagem descontínuas em zonas desabrigadas: avaliação de ferramentas de cálculo existentes

Dissertação para obtenção do grau de Mestre em Engenharia Civil na Área de especialização em Hidráulica

P53 and Cancer-Associated Sialylated Glycans Are Surrogate Markers of Cancerization of the Bladder Associated with Schistosoma haematobium Infection

BACKGROUND: Bladder cancer is a significant health problem in rural areas of Africa and the Middle East where Schistosoma haematobium is prevalent, supporting an association between malignant transformation and infection by this blood fluke. Nevertheless, the molecular mechanisms linking these events are poorly understood. Bladder cancers in infected populations are generally diagnosed at a late stage since there is a lack of non-invasive diagnostic tools, hence enforcing the need for early carcinogenesis markers. METHODOLOGY/PRINCIPAL FINDINGS: Forty-three formalin-fixed paraffin-embedded bladder biopsies of S. haematobium-infected patients, consisting of bladder tumours, tumour adjacent mucosa and pre-malignant/malignant urothelial lesions, were screened for bladder cancer biomarkers. These included the oncoprotein p53, the tumour proliferation rate (Ki-67>17%), cell-surface cancer-associated glycan sialyl-Tn (sTn) and sialyl-Lewisa/x (sLea/sLex), involved in immune escape and metastasis. Bladder tumours of non-S. haematobium etiology and normal urothelium were used as controls. S. haematobium-associated benign/pre-malignant lesions present alterations in p53 and sLex that were also found in bladder tumors. Similar results were observed in non-S. haematobium associated tumours, irrespectively of their histological nature, denoting some common molecular pathways. In addition, most benign/pre-malignant lesions also expressed sLea. However, proliferative phenotypes were more prevalent in lesions adjacent to bladder tumors while sLea was characteristic of sole benign/pre-malignant lesions, suggesting it may be a biomarker of early carcionogenesis associated with the parasite. A correlation was observed between the frequency of the biomarkers in the tumor and adjacent mucosa, with the exception of Ki-67. Most S. haematobium eggs embedded in the urothelium were also positive for sLea and sLex. Reinforcing the pathologic nature of the studied biomarkers, none was observed in the healthy urothelium. CONCLUSION/SIGNIFICANCE: This preliminary study suggests that p53 and sialylated glycans are surrogate biomarkers of bladder cancerization associated with S. haematobium, highlighting a missing link between infection and cancer development. Eggs of S. haematobium express sLea and sLex antigens in mimicry of human leukocytes glycosylation, which may play a role in the colonization and disease dissemination. These observations may help the early identification of infected patients at a higher risk of developing bladder cancer and guide the future development of non-invasive diagnostic tests.

Crise e democracia: resolução da crise e aprofundamento da democracia

Capítulo do livro Investigação e prática em economia