Diorganoruthenium complexes incorporating noninnocent [C6H2(CH2ER2)2-3,5]22-(E = N, P) Bis-Pincer bridging ligands: synthesis, spectroelectrochemistry, and DFT studies

The dinuclear complex [(tpy)Ru-II(PCP-PCP)Ru-II(tPY)]Cl-2 (bridging PCP-PCP = 3,3',5,5'-tetrakis(diphenylphosphinomethyl)biphenyl, [C6H2(CH2PPh2)(2)-3,5](2)(2-)) was prepared via a transcyclometalation reaction of the bis-pincer ligand [PC(H)P-PC(H)P] and the Ru(II) precursor [Ru(NCN)(tpy)]Cl (NCN = [C6H3(CH2NMe2)(2)-2,6](-)) followed by a reaction with 2,2':6',2 ''-terpyridine (tpy). Electrochemical and spectroscopic properties of [(tpy)Ru-II(PCP-PCP)Ru-II(tPY)]Cl-2 are compared with those of the closely related [(tpy)Ru-II(NCN-NCN)Ru-II(tpy)](PF6)(2) (NCN-NCN = [C6H2(CH2- NMe2)(2)-3,5](2)(2-)) obtained by two-electron reduction of [(tpy)Ru-III(NCN-NCN)Ru-III(tpy)](PF6)(4). The molecular structure of the latter complex has been determined by single-crystal X-ray structure determination. One-electron reduction of [(tpy)Ru-III(NCN-NCN)Ru-III(tpy)](PF6)(4) and one-electron oxidation of [(tpy)Ru-II(PCP-PCP)RUII(tpy)]Cl-2 yielded the mixed-valence species [(tpy)Ru-III(NCN-NCN)RUII(tpy)](3+) and [(tpy)Ru-III(PCP-PCP)RUII(tpy)](3+), respectively. The comproportionation equilibrium constants K-c (900 and 748 for [(tpy)Ru-III(NCN-NCN)Ru-III(tpy)](4+) and [(tpy)Ru-II(PCP-PCP)RUII(tpy)](2+), respectively) determined from cyclic voltammetric data reveal comparable stability of the [Ru-III-Ru-II] state of both complexes. Spectroelectrochemical measurements and near-infrared (NIR) spectroscopy were employed to further characterize the different redox states with special focus on the mixed-valence species and their NIR bands. Analysis of these bands in the framework of Hush theory indicates that the mixed-valence complexes [(tpy)Ru-III(PCP-PCP)RUII(tpy)](3+) and [(tpy)Ru-III(NCN-NCN)RUII(tpy)](3+) belong to strongly coupled borderline Class II/Class III and intrinsically coupled Class III systems, respectively. Preliminary DFT calculations suggest that extensive delocalization of the spin density over the metal centers and the bridging ligand exists. TD-DFT calculations then suggested a substantial MLCT character of the NIR electronic transitions. The results obtained in this study point to a decreased metal-metal electronic interaction accommodated by the double-cyclometalated bis-pincer bridge when strong sigma-donor NMe2 groups are replaced by weak sigma-donor, pi-acceptor PPh2 groups

The generation of scenes in mixed reality environments using the chromakey technique

A classic problem in the development of Mixed Reality systems is the registration. The correct alignment between virtual objects and the real elements is extremely important for the coherent composition of the resultant scene. Considering this context, this paper describes an approach for the composition of scenes in Mixed Reality environments using the chromakey technique for the extraction of real objects. After that, the scene is mounted in a coherent way related to the depth in OpenGL framebuffer for posterior rendering. ©2007 IEEE.

Multimetallic complexes based on phosphine- and phosphine oxide- appended p-hydroquinones

Presented here, is the work done with a series of binucleating ligands based on phosphine and phosphine oxide appended p-hydroquinones and their reactions towards various metals sources. The long term goal of the project was to produce coordination polymers that would have novel electronic, magnetic, and optical properties which would be of use in the field of molecular electronics. Binucleating ligands contained a p-hydroquinone motif in which various phosphine- and phosphine oxide substituents have been placed in the ortho position relative to each of the hydroxy position were synthesized. A previously published synthetic method for such lugands utilized n-BuLi to form a phenyl lithium intermediate which was quenched with chlorodiphenylphosphine. This technique was also used to produce a ligand with diisopropylphosphine groups. Phosphine ligands, containing the same structural motif, were also generated using LDA as the lithiating agent. This technique was found to be higher yielding. Phosphine chalcogenide ligands were accessed by further oxidizing the low valent phosphorous centers with either hydrogen peroxide or with elemental sulfur. These ligands were characterized using multinuclear NMR, low and high resolution mass spectroscopy, FTIR, and single crystal X-ray diffraction. Their electrochemical properties were explored with cyclic voltammetry. The phosphine appended ligands were used in the synthesis of a several bimetallic complexes. It was found that the ligands readily reacted with NiCp2 and NiCp*2, displacing one of the cyclopentadiene (Cp) or pentamethylcyclopentadiene (Cp*) rings. A cyclopentadiene complexes, containing diisopropylphine, was readily oxidized by[FeCp2]PF6 to give a NMR silent mixed valence complex. Cyclic voltammetry of these complexes showed a number of reversible waves with a large potential separation. The mixed valence compounds also showed a large absorbance band in the NIR region which was assigned to be an intervalence charge transfer. The cyclic voltammetry and NIR spectroscopy suggest that these systems are very capable of efficient metal-to-metal charge transfer. These complexes were characterized by multinuclear NMR, single crystal X-ray diffraction, UV/VIS-NIR spectroscopy and elemental analysis. The phosphine oxide ligands were reacted with a variety of different metal sources but limited success was gained in obtaining single crystals, allowing structural characterization of these compounds. Single crystals were obtained from products generated by reacting the diphenylphosphine oxide ligand with (Bipy)Cu(NO3)2 and Cu(NO3)2. In all cases the ligand had been further oxidized to a 2,5-dihydroxy-1,4-benzoquinone motif. In the reaction between the diphenylphosphine oxide ligand and (Bipy)Cu(NO3)2 it was found that the phosphine oxide moiety was involved with intermolecular coordination leading to the formation of a one-dimensional polymer composed of a series of bimetallic complexes tethered together. When NaSbF6 was present in the reaction with (Bipy)Cu(NO3)2 a unique tetrametallic complex was formed. Here the phospine oxide moiety was oriented so that two bimetallic complexes were bound together. If only Cu(NO3)2 was present, a two-dimensional polymeric sheet was formed where the ligand was present in two different coordination modes. The electronic properties of these complexes remained to be assessed.

The MIRELA framework: modeling and analyzing mixed reality applications using timed automata

Mixed Reality (MR) aims to link virtual entities with the real world and has many applications such as military and medical domains [JBL+00, NFB07]. In many MR systems and more precisely in augmented scenes, one needs the application to render the virtual part accurately at the right time. To achieve this, such systems acquire data related to the real world from a set of sensors before rendering virtual entities. A suitable system architecture should minimize the delays to keep the overall system delay (also called end-to-end latency) within the requirements for real-time performance. In this context, we propose a compositional modeling framework for MR software architectures in order to specify, simulate and validate formally the time constraints of such systems. Our approach is first based on a functional decomposition of such systems into generic components. The obtained elements as well as their typical interactions give rise to generic representations in terms of timed automata. A whole system is then obtained as a composition of such defined components. To write specifications, a textual language named MIRELA (MIxed REality LAnguage) is proposed along with the corresponding compilation tools. The generated output contains timed automata in UPPAAL format for simulation and verification of time constraints. These automata may also be used to generate source code skeletons for an implementation on a MR platform. The approach is illustrated first on a small example. A realistic case study is also developed. It is modeled by several timed automata synchronizing through channels and including a large number of time constraints. Both systems have been simulated in UPPAAL and checked against the required behavioral properties.

Strategic Incentives in Unconventional Electoral Systems: Introduction to the Special Issue

The study of strategic behaviour and the impact of institutions on elections has mainly focused on simple and conventional electoral systems: list-proportional electoral systems (PR) and the plurality vote. Less conventional systems are not on the agenda of comparative studies, even though no less than 30% of countries use unconventional electoral systems for their national parliamentary elections, such as the Single Transferable Vote, PR with majority bonuses, or mixed electoral systems. Often, they provide for unusual combinations of different institutional incentives, and hence to particular actor strategies.

On real-time partitioned multicore systems

Partitioning is a common approach to developing mixed-criticality systems, where partitions are isolated from each other both in the temporal and the spatial domain in order to prevent low-criticality subsystems from compromising other subsystems with high level of criticality in case of misbehaviour. The advent of many-core processors, on the other hand, opens the way to highly parallel systems in which all partitions can be allocated to dedicated processor cores. This trend will simplify processor scheduling, although other issues such as mutual interference in the temporal domain may arise as a consequence of memory and device sharing. The paper describes an architecture for multi-core partitioned systems including critical subsystems built with the Ada Ravenscar profile. Some implementation issues are discussed, and experience on implementing the ORK kernel on the XtratuM partitioning hypervisor is presented.

Mixed-criticality design of a satellite software system

The continuous increment of processors computational power and the requirements on additional functionality and services are motivating a change in the way embedded systems are built. Components with different criticality level are allocated in the same processor, which give rise to mixed-criticality systems. The use of partitioned systems is a way of preventing undesirable interferences between components with different criticality level. An hypervisor provides these partitions or virtual machines, ensuring spatial, temporal and fault isolation between them. The purpose of this paper is to illustrate the development of a mixed-critical system. The attitude control subsystem is used for showing the different steps, which are supported by a toolset developed in the context of the MultiPARTES research project.

Run-Time Dynamically-Adaptable FPGA-Based Architecture for High-Performance Autonomous Distributed Systems

Esta tesis doctoral se enmarca dentro del campo de los sistemas embebidos reconfigurables, redes de sensores inalámbricas para aplicaciones de altas prestaciones, y computación distribuida. El documento se centra en el estudio de alternativas de procesamiento para sistemas embebidos autónomos distribuidos de altas prestaciones (por sus siglas en inglés, High-Performance Autonomous Distributed Systems (HPADS)), así como su evolución hacia el procesamiento de alta resolución. El estudio se ha llevado a cabo tanto a nivel de plataforma como a nivel de las arquitecturas de procesamiento dentro de la plataforma con el objetivo de optimizar aspectos tan relevantes como la eficiencia energética, la capacidad de cómputo y la tolerancia a fallos del sistema. Los HPADS son sistemas realimentados, normalmente formados por elementos distribuidos conectados o no en red, con cierta capacidad de adaptación, y con inteligencia suficiente para llevar a cabo labores de prognosis y/o autoevaluación. Esta clase de sistemas suele formar parte de sistemas más complejos llamados sistemas ciber-físicos (por sus siglas en inglés, Cyber-Physical Systems (CPSs)). Los CPSs cubren un espectro enorme de aplicaciones, yendo desde aplicaciones médicas, fabricación, o aplicaciones aeroespaciales, entre otras muchas. Para el diseño de este tipo de sistemas, aspectos tales como la confiabilidad, la definición de modelos de computación, o el uso de metodologías y/o herramientas que faciliten el incremento de la escalabilidad y de la gestión de la complejidad, son fundamentales. La primera parte de esta tesis doctoral se centra en el estudio de aquellas plataformas existentes en el estado del arte que por sus características pueden ser aplicables en el campo de los CPSs, así como en la propuesta de un nuevo diseño de plataforma de altas prestaciones que se ajuste mejor a los nuevos y más exigentes requisitos de las nuevas aplicaciones. Esta primera parte incluye descripción, implementación y validación de la plataforma propuesta, así como conclusiones sobre su usabilidad y sus limitaciones. Los principales objetivos para el diseño de la plataforma propuesta se enumeran a continuación: • Estudiar la viabilidad del uso de una FPGA basada en RAM como principal procesador de la plataforma en cuanto a consumo energético y capacidad de cómputo. • Propuesta de técnicas de gestión del consumo de energía en cada etapa del perfil de trabajo de la plataforma. •Propuestas para la inclusión de reconfiguración dinámica y parcial de la FPGA (por sus siglas en inglés, Dynamic Partial Reconfiguration (DPR)) de forma que sea posible cambiar ciertas partes del sistema en tiempo de ejecución y sin necesidad de interrumpir al resto de las partes. Evaluar su aplicabilidad en el caso de HPADS. Las nuevas aplicaciones y nuevos escenarios a los que se enfrentan los CPSs, imponen nuevos requisitos en cuanto al ancho de banda necesario para el procesamiento de los datos, así como en la adquisición y comunicación de los mismos, además de un claro incremento en la complejidad de los algoritmos empleados. Para poder cumplir con estos nuevos requisitos, las plataformas están migrando desde sistemas tradicionales uni-procesador de 8 bits, a sistemas híbridos hardware-software que incluyen varios procesadores, o varios procesadores y lógica programable. Entre estas nuevas arquitecturas, las FPGAs y los sistemas en chip (por sus siglas en inglés, System on Chip (SoC)) que incluyen procesadores embebidos y lógica programable, proporcionan soluciones con muy buenos resultados en cuanto a consumo energético, precio, capacidad de cómputo y flexibilidad. Estos buenos resultados son aún mejores cuando las aplicaciones tienen altos requisitos de cómputo y cuando las condiciones de trabajo son muy susceptibles de cambiar en tiempo real. La plataforma propuesta en esta tesis doctoral se ha denominado HiReCookie. La arquitectura incluye una FPGA basada en RAM como único procesador, así como un diseño compatible con la plataforma para redes de sensores inalámbricas desarrollada en el Centro de Electrónica Industrial de la Universidad Politécnica de Madrid (CEI-UPM) conocida como Cookies. Esta FPGA, modelo Spartan-6 LX150, era, en el momento de inicio de este trabajo, la mejor opción en cuanto a consumo y cantidad de recursos integrados, cuando además, permite el uso de reconfiguración dinámica y parcial. Es importante resaltar que aunque los valores de consumo son los mínimos para esta familia de componentes, la potencia instantánea consumida sigue siendo muy alta para aquellos sistemas que han de trabajar distribuidos, de forma autónoma, y en la mayoría de los casos alimentados por baterías. Por esta razón, es necesario incluir en el diseño estrategias de ahorro energético para incrementar la usabilidad y el tiempo de vida de la plataforma. La primera estrategia implementada consiste en dividir la plataforma en distintas islas de alimentación de forma que sólo aquellos elementos que sean estrictamente necesarios permanecerán alimentados, cuando el resto puede estar completamente apagado. De esta forma es posible combinar distintos modos de operación y así optimizar enormemente el consumo de energía. El hecho de apagar la FPGA para ahora energía durante los periodos de inactividad, supone la pérdida de la configuración, puesto que la memoria de configuración es una memoria volátil. Para reducir el impacto en el consumo y en el tiempo que supone la reconfiguración total de la plataforma una vez encendida, en este trabajo, se incluye una técnica para la compresión del archivo de configuración de la FPGA, de forma que se consiga una reducción del tiempo de configuración y por ende de la energía consumida. Aunque varios de los requisitos de diseño pueden satisfacerse con el diseño de la plataforma HiReCookie, es necesario seguir optimizando diversos parámetros tales como el consumo energético, la tolerancia a fallos y la capacidad de procesamiento. Esto sólo es posible explotando todas las posibilidades ofrecidas por la arquitectura de procesamiento en la FPGA. Por lo tanto, la segunda parte de esta tesis doctoral está centrada en el diseño de una arquitectura reconfigurable denominada ARTICo3 (Arquitectura Reconfigurable para el Tratamiento Inteligente de Cómputo, Confiabilidad y Consumo de energía) para la mejora de estos parámetros por medio de un uso dinámico de recursos. ARTICo3 es una arquitectura de procesamiento para FPGAs basadas en RAM, con comunicación tipo bus, preparada para dar soporte para la gestión dinámica de los recursos internos de la FPGA en tiempo de ejecución gracias a la inclusión de reconfiguración dinámica y parcial. Gracias a esta capacidad de reconfiguración parcial, es posible adaptar los niveles de capacidad de procesamiento, energía consumida o tolerancia a fallos para responder a las demandas de la aplicación, entorno, o métricas internas del dispositivo mediante la adaptación del número de recursos asignados para cada tarea. Durante esta segunda parte de la tesis se detallan el diseño de la arquitectura, su implementación en la plataforma HiReCookie, así como en otra familia de FPGAs, y su validación por medio de diferentes pruebas y demostraciones. Los principales objetivos que se plantean la arquitectura son los siguientes: • Proponer una metodología basada en un enfoque multi-hilo, como las propuestas por CUDA (por sus siglas en inglés, Compute Unified Device Architecture) u Open CL, en la cual distintos kernels, o unidades de ejecución, se ejecuten en un numero variable de aceleradores hardware sin necesidad de cambios en el código de aplicación. • Proponer un diseño y proporcionar una arquitectura en la que las condiciones de trabajo cambien de forma dinámica dependiendo bien de parámetros externos o bien de parámetros que indiquen el estado de la plataforma. Estos cambios en el punto de trabajo de la arquitectura serán posibles gracias a la reconfiguración dinámica y parcial de aceleradores hardware en tiempo real. • Explotar las posibilidades de procesamiento concurrente, incluso en una arquitectura basada en bus, por medio de la optimización de las transacciones en ráfaga de datos hacia los aceleradores. •Aprovechar las ventajas ofrecidas por la aceleración lograda por módulos puramente hardware para conseguir una mejor eficiencia energética. • Ser capaces de cambiar los niveles de redundancia de hardware de forma dinámica según las necesidades del sistema en tiempo real y sin cambios para el código de aplicación. • Proponer una capa de abstracción entre el código de aplicación y el uso dinámico de los recursos de la FPGA. El diseño en FPGAs permite la utilización de módulos hardware específicamente creados para una aplicación concreta. De esta forma es posible obtener rendimientos mucho mayores que en el caso de las arquitecturas de propósito general. Además, algunas FPGAs permiten la reconfiguración dinámica y parcial de ciertas partes de su lógica en tiempo de ejecución, lo cual dota al diseño de una gran flexibilidad. Los fabricantes de FPGAs ofrecen arquitecturas predefinidas con la posibilidad de añadir bloques prediseñados y poder formar sistemas en chip de una forma más o menos directa. Sin embargo, la forma en la que estos módulos hardware están organizados dentro de la arquitectura interna ya sea estática o dinámicamente, o la forma en la que la información se intercambia entre ellos, influye enormemente en la capacidad de cómputo y eficiencia energética del sistema. De la misma forma, la capacidad de cargar módulos hardware bajo demanda, permite añadir bloques redundantes que permitan aumentar el nivel de tolerancia a fallos de los sistemas. Sin embargo, la complejidad ligada al diseño de bloques hardware dedicados no debe ser subestimada. Es necesario tener en cuenta que el diseño de un bloque hardware no es sólo su propio diseño, sino también el diseño de sus interfaces, y en algunos casos de los drivers software para su manejo. Además, al añadir más bloques, el espacio de diseño se hace más complejo, y su programación más difícil. Aunque la mayoría de los fabricantes ofrecen interfaces predefinidas, IPs (por sus siglas en inglés, Intelectual Property) comerciales y plantillas para ayudar al diseño de los sistemas, para ser capaces de explotar las posibilidades reales del sistema, es necesario construir arquitecturas sobre las ya establecidas para facilitar el uso del paralelismo, la redundancia, y proporcionar un entorno que soporte la gestión dinámica de los recursos. Para proporcionar este tipo de soporte, ARTICo3 trabaja con un espacio de soluciones formado por tres ejes fundamentales: computación, consumo energético y confiabilidad. De esta forma, cada punto de trabajo se obtiene como una solución de compromiso entre estos tres parámetros. Mediante el uso de la reconfiguración dinámica y parcial y una mejora en la transmisión de los datos entre la memoria principal y los aceleradores, es posible dedicar un número variable de recursos en el tiempo para cada tarea, lo que hace que los recursos internos de la FPGA sean virtualmente ilimitados. Este variación en el tiempo del número de recursos por tarea se puede usar bien para incrementar el nivel de paralelismo, y por ende de aceleración, o bien para aumentar la redundancia, y por lo tanto el nivel de tolerancia a fallos. Al mismo tiempo, usar un numero óptimo de recursos para una tarea mejora el consumo energético ya que bien es posible disminuir la potencia instantánea consumida, o bien el tiempo de procesamiento. Con el objetivo de mantener los niveles de complejidad dentro de unos límites lógicos, es importante que los cambios realizados en el hardware sean totalmente transparentes para el código de aplicación. A este respecto, se incluyen distintos niveles de transparencia: • Transparencia a la escalabilidad: los recursos usados por una misma tarea pueden ser modificados sin que el código de aplicación sufra ningún cambio. • Transparencia al rendimiento: el sistema aumentara su rendimiento cuando la carga de trabajo aumente, sin cambios en el código de aplicación. • Transparencia a la replicación: es posible usar múltiples instancias de un mismo módulo bien para añadir redundancia o bien para incrementar la capacidad de procesamiento. Todo ello sin que el código de aplicación cambie. • Transparencia a la posición: la posición física de los módulos hardware es arbitraria para su direccionamiento desde el código de aplicación. • Transparencia a los fallos: si existe un fallo en un módulo hardware, gracias a la redundancia, el código de aplicación tomará directamente el resultado correcto. • Transparencia a la concurrencia: el hecho de que una tarea sea realizada por más o menos bloques es transparente para el código que la invoca. Por lo tanto, esta tesis doctoral contribuye en dos líneas diferentes. En primer lugar, con el diseño de la plataforma HiReCookie y en segundo lugar con el diseño de la arquitectura ARTICo3. Las principales contribuciones de esta tesis se resumen a continuación. • Arquitectura de la HiReCookie incluyendo: o Compatibilidad con la plataforma Cookies para incrementar las capacidades de esta. o División de la arquitectura en distintas islas de alimentación. o Implementación de los diversos modos de bajo consumo y políticas de despertado del nodo. o Creación de un archivo de configuración de la FPGA comprimido para reducir el tiempo y el consumo de la configuración inicial. • Diseño de la arquitectura reconfigurable para FPGAs basadas en RAM ARTICo3: o Modelo de computación y modos de ejecución inspirados en el modelo de CUDA pero basados en hardware reconfigurable con un número variable de bloques de hilos por cada unidad de ejecución. o Estructura para optimizar las transacciones de datos en ráfaga proporcionando datos en cascada o en paralelo a los distinto módulos incluyendo un proceso de votado por mayoría y operaciones de reducción. o Capa de abstracción entre el procesador principal que incluye el código de aplicación y los recursos asignados para las diferentes tareas. o Arquitectura de los módulos hardware reconfigurables para mantener la escalabilidad añadiendo una la interfaz para las nuevas funcionalidades con un simple acceso a una memoria RAM interna. o Caracterización online de las tareas para proporcionar información a un módulo de gestión de recursos para mejorar la operación en términos de energía y procesamiento cuando además se opera entre distintos nieles de tolerancia a fallos. El documento está dividido en dos partes principales formando un total de cinco capítulos. En primer lugar, después de motivar la necesidad de nuevas plataformas para cubrir las nuevas aplicaciones, se detalla el diseño de la plataforma HiReCookie, sus partes, las posibilidades para bajar el consumo energético y se muestran casos de uso de la plataforma así como pruebas de validación del diseño. La segunda parte del documento describe la arquitectura reconfigurable, su implementación en varias FPGAs, y pruebas de validación en términos de capacidad de procesamiento y consumo energético, incluyendo cómo estos aspectos se ven afectados por el nivel de tolerancia a fallos elegido. Los capítulos a lo largo del documento son los siguientes: El capítulo 1 analiza los principales objetivos, motivación y aspectos teóricos necesarios para seguir el resto del documento. El capítulo 2 está centrado en el diseño de la plataforma HiReCookie y sus posibilidades para disminuir el consumo de energía. El capítulo 3 describe la arquitectura reconfigurable ARTICo3. El capítulo 4 se centra en las pruebas de validación de la arquitectura usando la plataforma HiReCookie para la mayoría de los tests. Un ejemplo de aplicación es mostrado para analizar el funcionamiento de la arquitectura. El capítulo 5 concluye esta tesis doctoral comentando las conclusiones obtenidas, las contribuciones originales del trabajo y resultados y líneas futuras. ABSTRACT This PhD Thesis is framed within the field of dynamically reconfigurable embedded systems, advanced sensor networks and distributed computing. The document is centred on the study of processing solutions for high-performance autonomous distributed systems (HPADS) as well as their evolution towards High performance Computing (HPC) systems. The approach of the study is focused on both platform and processor levels to optimise critical aspects such as computing performance, energy efficiency and fault tolerance. HPADS are considered feedback systems, normally networked and/or distributed, with real-time adaptive and predictive functionality. These systems, as part of more complex systems known as Cyber-Physical Systems (CPSs), can be applied in a wide range of fields such as military, health care, manufacturing, aerospace, etc. For the design of HPADS, high levels of dependability, the definition of suitable models of computation, and the use of methodologies and tools to support scalability and complexity management, are required. The first part of the document studies the different possibilities at platform design level in the state of the art, together with description, development and validation tests of the platform proposed in this work to cope with the previously mentioned requirements. The main objectives targeted by this platform design are the following: • Study the feasibility of using SRAM-based FPGAs as the main processor of the platform in terms of energy consumption and performance for high demanding applications. • Analyse and propose energy management techniques to reduce energy consumption in every stage of the working profile of the platform. • Provide a solution with dynamic partial and wireless remote HW reconfiguration (DPR) to be able to change certain parts of the FPGA design at run time and on demand without interrupting the rest of the system. • Demonstrate the applicability of the platform in different test-bench applications. In order to select the best approach for the platform design in terms of processing alternatives, a study of the evolution of the state-of-the-art platforms is required to analyse how different architectures cope with new more demanding applications and scenarios: security, mixed-critical systems for aerospace, multimedia applications, or military environments, among others. In all these scenarios, important changes in the required processing bandwidth or the complexity of the algorithms used are provoking the migration of the platforms from single microprocessor architectures to multiprocessing and heterogeneous solutions with more instant power consumption but higher energy efficiency. Within these solutions, FPGAs and Systems on Chip including FPGA fabric and dedicated hard processors, offer a good trade of among flexibility, processing performance, energy consumption and price, when they are used in demanding applications where working conditions are very likely to vary over time and high complex algorithms are required. The platform architecture proposed in this PhD Thesis is called HiReCookie. It includes an SRAM-based FPGA as the main and only processing unit. The FPGA selected, the Xilinx Spartan-6 LX150, was at the beginning of this work the best choice in terms of amount of resources and power. Although, the power levels are the lowest of these kind of devices, they can be still very high for distributed systems that normally work powered by batteries. For that reason, it is necessary to include different energy saving possibilities to increase the usability of the platform. In order to reduce energy consumption, the platform architecture is divided into different power islands so that only those parts of the systems that are strictly needed are powered on, while the rest of the islands can be completely switched off. This allows a combination of different low power modes to decrease energy. In addition, one of the most important handicaps of SRAM-based FPGAs is that they are not alive at power up. Therefore, recovering the system from a switch-off state requires to reload the FPGA configuration from a non-volatile memory device. For that reason, this PhD Thesis also proposes a methodology to compress the FPGA configuration file in order to reduce time and energy during the initial configuration process. Although some of the requirements for the design of HPADS are already covered by the design of the HiReCookie platform, it is necessary to continue improving energy efficiency, computing performance and fault tolerance. This is only possible by exploiting all the opportunities provided by the processing architectures configured inside the FPGA. Therefore, the second part of the thesis details the design of the so called ARTICo3 FPGA architecture to enhance the already intrinsic capabilities of the FPGA. ARTICo3 is a DPR-capable bus-based virtual architecture for multiple HW acceleration in SRAM-based FPGAs. The architecture provides support for dynamic resource management in real time. In this way, by using DPR, it will be possible to change the levels of computing performance, energy consumption and fault tolerance on demand by increasing or decreasing the amount of resources used by the different tasks. Apart from the detailed design of the architecture and its implementation in different FPGA devices, different validation tests and comparisons are also shown. The main objectives targeted by this FPGA architecture are listed as follows: • Provide a method based on a multithread approach such as those offered by CUDA (Compute Unified Device Architecture) or OpenCL kernel executions, where kernels are executed in a variable number of HW accelerators without requiring application code changes. • Provide an architecture to dynamically adapt working points according to either self-measured or external parameters in terms of energy consumption, fault tolerance and computing performance. Taking advantage of DPR capabilities, the architecture must provide support for a dynamic use of resources in real time. • Exploit concurrent processing capabilities in a standard bus-based system by optimizing data transactions to and from HW accelerators. • Measure the advantage of HW acceleration as a technique to boost performance to improve processing times and save energy by reducing active times for distributed embedded systems. • Dynamically change the levels of HW redundancy to adapt fault tolerance in real time. • Provide HW abstraction from SW application design. FPGAs give the possibility of designing specific HW blocks for every required task to optimise performance while some of them include the possibility of including DPR. Apart from the possibilities provided by manufacturers, the way these HW modules are organised, addressed and multiplexed in area and time can improve computing performance and energy consumption. At the same time, fault tolerance and security techniques can also be dynamically included using DPR. However, the inherent complexity of designing new HW modules for every application is not negligible. It does not only consist of the HW description, but also the design of drivers and interfaces with the rest of the system, while the design space is widened and more complex to define and program. Even though the tools provided by the majority of manufacturers already include predefined bus interfaces, commercial IPs, and templates to ease application prototyping, it is necessary to improve these capabilities. By adding new architectures on top of them, it is possible to take advantage of parallelization and HW redundancy while providing a framework to ease the use of dynamic resource management. ARTICo3 works within a solution space where working points change at run time in a 3D space defined by three different axes: Computation, Consumption, and Fault Tolerance. Therefore, every working point is found as a trade-off solution among these three axes. By means of DPR, different accelerators can be multiplexed so that the amount of available resources for any application is virtually unlimited. Taking advantage of DPR capabilities and a novel way of transmitting data to the reconfigurable HW accelerators, it is possible to dedicate a dynamically-changing number of resources for a given task in order to either boost computing speed or adding HW redundancy and a voting process to increase fault-tolerance levels. At the same time, using an optimised amount of resources for a given task reduces energy consumption by reducing instant power or computing time. In order to keep level complexity under certain limits, it is important that HW changes are transparent for the application code. Therefore, different levels of transparency are targeted by the system: • Scalability transparency: a task must be able to expand its resources without changing the system structure or application algorithms. • Performance transparency: the system must reconfigure itself as load changes. • Replication transparency: multiple instances of the same task are loaded to increase reliability and performance. • Location transparency: resources are accessed with no knowledge of their location by the application code. • Failure transparency: task must be completed despite a failure in some components. • Concurrency transparency: different tasks will work in a concurrent way transparent to the application code. Therefore, as it can be seen, the Thesis is contributing in two different ways. First with the design of the HiReCookie platform and, second with the design of the ARTICo3 architecture. The main contributions of this PhD Thesis are then listed below: • Architecture of the HiReCookie platform including: o Compatibility of the processing layer for high performance applications with the Cookies Wireless Sensor Network platform for fast prototyping and implementation. o A division of the architecture in power islands. o All the different low-power modes. o The creation of the partial-initial bitstream together with the wake-up policies of the node. • The design of the reconfigurable architecture for SRAM FPGAs: ARTICo3: o A model of computation and execution modes inspired in CUDA but based on reconfigurable HW with a dynamic number of thread blocks per kernel. o A structure to optimise burst data transactions providing coalesced or parallel data to HW accelerators, parallel voting process and reduction operation. o The abstraction provided to the host processor with respect to the operation of the kernels in terms of the number of replicas, modes of operation, location in the reconfigurable area and addressing. o The architecture of the modules representing the thread blocks to make the system scalable by adding functional units only adding an access to a BRAM port. o The online characterization of the kernels to provide information to a scheduler or resource manager in terms of energy consumption and processing time when changing among different fault-tolerance levels, as well as if a kernel is expected to work in the memory-bounded or computing-bounded areas. The document of the Thesis is divided into two main parts with a total of five chapters. First, after motivating the need for new platforms to cover new more demanding applications, the design of the HiReCookie platform, its parts and several partial tests are detailed. The design of the platform alone does not cover all the needs of these applications. Therefore, the second part describes the architecture inside the FPGA, called ARTICo3, proposed in this PhD Thesis. The architecture and its implementation are tested in terms of energy consumption and computing performance showing different possibilities to improve fault tolerance and how this impact in energy and time of processing. Chapter 1 shows the main goals of this PhD Thesis and the technology background required to follow the rest of the document. Chapter 2 shows all the details about the design of the FPGA-based platform HiReCookie. Chapter 3 describes the ARTICo3 architecture. Chapter 4 is focused on the validation tests of the ARTICo3 architecture. An application for proof of concept is explained where typical kernels related to image processing and encryption algorithms are used. Further experimental analyses are performed using these kernels. Chapter 5 concludes the document analysing conclusions, comments about the contributions of the work, and some possible future lines for the work.

Manifestation of Colossal Thermoelectric Power by Charge Ordered Small and Intermediate Bandwidth Manganites

Thermoelectric materials are revisited for various applications including power generation. The direct conversion of temperature differences into electric voltage and vice versa is known as thermoelectric effect. Possible applications of thermoelectric materials are in eco-friendly refrigeration, electric power generation from waste heat, infrared sensors, temperature controlled-seats and portable picnic coolers. Thermoelectric materials are also extensively researched upon as an alternative to compression based refrigeration. This utilizes the principle of Peltier cooling. The performance characteristic of a thermoelectric material, termed as figure of merit (ZT) is a function of several transport coefficients such as electrical conductivity (σ), thermal conductivity (κ) and Seebeck coefficient of the material (S). ZT is expressed asκσTZTS2=, where T is the temperature in degree absolute. A large value of Seebeck coefficient, high electrical conductivity and low thermal conductivity are necessary to realize a high performance thermoelectric material. The best known thermoelectric materials are phonon-glass electron – crystal (PGEC) system where the phonons are scattered within the unit cell by the rattling structure and electrons are scattered less as in crystals to obtain a high electrical conductivity. A survey of literature reveals that correlated semiconductors and Kondo insulators containing rare earth or transition metal ions are found to be potential thermoelectric materials. The structural magnetic and charge transport properties in manganese oxides having the general formula of RE1−xAExMnO3 (RE = rare earth, AE= Ca, Sr, Ba) are solely determined by the mixed valence (3+/4+) state of Mn ions. In strongly correlated electron systems, magnetism and charge transport properties are strongly correlated. Within the area of strongly correlated electron systems the study of manganese oxides, widely known as manganites exhibit unique magneto electric transport properties, is an active area of research.Strongly correlated systems like perovskite manganites, characterized by their narrow localized band and hoping conduction, were found to be good candidates for thermoelectric applications. Manganites represent a highly correlated electron system and exhibit a variety of phenomena such as charge, orbital and magnetic ordering, colossal magneto resistance and Jahn-Teller effect. The strong inter-dependence between the magnetic order parameters and the transport coefficients in manganites has generated much research interest in the thermoelectric properties of manganites. Here, large thermal motion or rattling of rare earth atoms with localized magnetic moments is believed to be responsible for low thermal conductivity of these compounds. The 4f levels in these compounds, lying near the Fermi energy, create large density of states at the Fermi level and hence they are likely to exhibit a fairly large value of Seebeck coefficient.

Trapping phosphorus (III) into polyoxometalates: synthesis, characterisation and electronic behaviour study

The introduction of electronically-active heteroanions into polyoxometalates (POMs) is one of the emerging topics in this field. The novel clusters have shown unprecedented intramolecular electron-transfer features that can be directly mediated by the incorporated heteroanions. In this thesis, we will focus on the study of phosphite (HPO32-) as new non-traditional heteroanions, discover HPO32- templated nanostructures, investigate their electronic behaviours as well as understand the self-assembly process of HPO32--templated species. The thesis starts with incorporating HPO32- into POM cages. The feasibility of this work was illustrated by the successful trapping of HPO32- into a “Trojan Horse” type {W18O56} nanocage. The reactivity of embedded {HPO3} was fully studied, showing the cluster undergoes a structural rearrangement in solution whereby the {HPO3} moieties dimerise to form a weakly interacting (O3PH···HPO3) moiety. In the crystalline state a temperature-dependent intramolecular redox reaction and structural rearrangement occurs. This rearrangement appears to proceed via an intermediate containing two different templates, a pyramidal {HPO3} and a tetrahedral {PO4} moiety. {HPO3} templated POM cages were then vigorously expanded and led to the isolation of five either fully oxidised or mixed-valence clusters trapped with mono-, di-, or tri- {HPO3}. Interestingly, an intriguing 3D honeycomb-like host-guest structure was also synthesised. The porous framework was self-aggregated by a tri-phopshite anion templated {W21} cluster with a {VO4} templated Wells-Dawson type {W18} acting as a guest species within the hexagonal channels. Based on this work, we further extended the templating anions to two different redox-active heteroanions, and discovered a unique mixed-heteroatom templated system built by pairing redox-active {HPIIIO3} with {TeO3}, {SeO3} or {AsO3}. Two molecular systems were developed, ie. “Trojan Horse” type [W18O56(HPO3)0.8(SeO3)1.2(H2O)2]8- and cross-shaped [H4P4X4W64O224]32-/36-, where X=TeIV, SeIV, AsIII. In the case of {W18(HPO3)0.8(SeO3)1.2}, the compound is found to be a mixture of heteroleptic {W18(HPO3)(SeO3)} and homoleptic {W18(SeO3)2} and {W18(HPO3)2}, identified by single crystal x-ray diffraction, NMR as well as high resolution mass spectrometry. The cluster exhibited similar temperature-dependent electronic features to “Trojan Horse” type {W18(HPO3)2O56}. However, due to the intrinsic reactivity difference between {HPO3} and {SeO3}, the thermal treatment leads to the formation of an unusual species [W18O55(PO4)(SeO3)]5-, in which {HPO3} was fully oxidised to {PO4} within the cage, whereas and lone-pair-containing {SeO3} heteroanions were kept intact inside the shell. This finding is extremely interesting, as it demonstrated that multiple and independent intramolecular electronic performance can be achieved by the coexistence of distinct heteroatoms within a single molecule. On the other hand, the cross-shaped [H4P4X4W64O224]32-/36- were constructed by four {W15(HPO3)(XO3)} building units linked by four {WO6} octahedra. Each building unit traps two different heteroatoms. It is interesting to note that the mixed heteroatom species show self-sorting, with a highly selective positional preference. Smaller ionic sized {HPO3} are self-organised into the uncapped side of {W15} cavity, whereas closed side are occupied by larger heteroatoms, which is surprisingly opposed to steric hindrance. Density functional theory (DFT) calculations are currently underway to have a full understanding of the preference of heteroatom substitutions. This series of clusters is of great interest in terms of achieving single molecule-based heteroatom-dependent multiple levels of electron transfer. It has opened a new way to design and synthesise POMs with higher diversity of electrical states, which may lead to a new type of Q-bits for quantum computing. The third chapter is focused on developing polyoxotungstate building blocks templated by {HPO3}. A series of building blocks, {W15O48(HPO3)2}, {W9O30(HPO3)} {W12O40(HPO3)2} and hexagonal {W6O18(HPO3)} have been obtained. The first four building blocks have been reported with {SeO3} and/or {TeO3} heteroanions. This result demonstrates {HPO3} has a similar reactivity as {SeO3} and {TeO3}, therefore studying the self-assembly of {HPO3}-based building blocks would be helpful to have a general understanding of pyramidal heteroatom-based molecular systems. The hexagonal {W6O18(HPO3)} is observed for the first time in polyoxotungstates, showing some of reactivity difference between {HPO3} and {SeO3} and {TeO3}. Furthermore, inorganic salts and pH values have some directing influence on the formation and transformation of various building blocks, resulting in the discovery of a family of {HPO3}-based clusters with nuclearity ranging from {W29} to {W106}. High resolution mass spectrometry was also carried out to investigate the cluster solution behaviour and also gain information of building block speciation. It is found that some clusters experienced decomposition, which gives rise to potential building blocks accountable for the self-assembly.

The first structurally characterized discrete dinuclear mu-cyano hexacyanoferrate complex

Mixed valence complexes containing ferro- and ferricyanide have been known for almost 300 years, but no dinuclear, non-polymeric examples of these complexes have been structurally characterized. Here we report the first such example, comprising ferrocyanide coordinated to a pentaaminecobalt(III) complex. This Fe-II-Co-III complex may be reversibly oxidized to the Fe-III-Co-III analogue.

Habitat structure and egg distributions in the processionary caterpillar Ochrogaster lunifer: lessons for conservation and pest management

1. The spatial and temporal distribution of eggs laid by herbivorous insects is a crucial component of herbivore population stability, as it influences overall mortality within the population. Thus an ecologist studying populations of an endangered butterfly can do little to increase its numbers through habitat management without knowledge of its egg-laying patterns across individual host-plants under different habitat management regimes. At the other end of the spectrum, a knowledge of egg-laying behaviour can do much to control pest outbreaks by disrupting egg distributions that lead to rapid population growth. 2. The distribution of egg batches of the processionary caterpillar Ochrogaster lunifer on acacia trees was monitored in 21 habitats during 2 years in coastal Australia. The presence of egg batches on acacias was affected by host-tree 'quality' (tree size and foliar chemistry that led to increased caterpillar survival) and host-tree 'apparency' (the amount of vegetation surrounding host-trees). 3. In open homogeneous habitats, more egg batches were laid on high-quality trees, increasing potential population growth. In diverse mixed-species habitats, more egg batches were laid on low-quality highly apparent trees, reducing population growth and so reducing the potential for unstable population dynamics. The aggregation of batches on small apparent trees in diverse habitats led to outbreaks on these trees year after year, even when population levels were low, while site-wide outbreaks were rare. 4. These results predict that diverse habitats with mixed plant species should increase insect aggregation and increase population stability. In contrast, in open disturbed habitats or in regular plantations, where egg batches are more evenly distributed across high-quality hosts, populations should be more unstable, with site-wide outbreaks and extinctions being more common. 5. Mixed planting should be used on habitat regeneration sites to increase the population stability of immigrating or reintroduced insect species. Mixed planting also increases the diversity of resources, leading to higher herbivore species richness. With regard to the conservation of single species, different practices of habitat management will need to be employed depending on whether a project is concerned with methods of rapidly increasing the abundance of an endangered insect or concerned with the maintenance of a stable, established insect population that is perhaps endemic to an area. Suggestions for habitat management in these different cases are discussed. 6. Finally, intercropping can be highly effective in reducing pest outbreaks, although the economic gains of reduced pest attack may be outweighed by reduced crop yields in mixed-crop systems.

Participatory assessment of rural livelihoods in the Central Highlands of Vietnam

There is a need for improved monitoring and evaluation (M&E) of participatory research with smallholder farmers, in particular to help differentiate between different types of farm household with different needs. This paper reports some of the results of a study to develop participatory M&E tools for the Forages for Smallholders Project in Southeast Asia, focusing on an upland commune in central Vietnam with a highly diverse crop-livestock system. Participatory rural appraisal techniques were used within a rural livelihoods framework to assess the differing livelihoods of poor, average, and better-off households. There were found to be marked differences between households, particularly in human resources, landholdings, and cattle numbers, affecting the livelihood strategies pursued. The improved understanding of livelihood strategies was gained in a cost-effective way and could be readily used by project participants to monitor the impacts of the introduced forages within the commune, enabling better focusing of the participatory research process on the needs and circumstances of poor farmers. (C) 2003 Elsevier Ltd. All rights reserved.

Ambient intelligence in emotion based ubiquitous decision making

As the time goes on, it is a question of common sense to involve in the process of decision making people scattered around the globe. Groups are created in a formal or informal way, exchange ideas or engage in a process of argumentation and counterargumentation, negotiate, cooperate, collaborate or even discuss techniques and/or methodologies for problem solving. In this work it is proposed an agent-based architecture to support a ubiquitous group decision support system, i.e. based on the concept of agent, which is able to exhibit intelligent, and emotional-aware behaviour, and support argumentation, through interaction with individual persons or groups. It is enforced the paradigm of Mixed Initiative Systems, so the initiative is to be pushed by human users and/or intelligent agents.