Petri Artedi renovati pars I. et II. [III-V] : i.e. bibliotheca et philosophia ichthyologica / cura Iohannis Iulii Walbaumii.

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Petri Artedi renovati pars I. et II. [III-V] : i.e. bibliotheca et philosophia ichthyologica / cura Iohannis Iulii Walbaumii.

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[Codicis Domini Iustiniani Sacratissimi Principis PP. Augusti repetitae praelectionis liber III [-V] /

Mode of access: Internet.

Investigation of electrically active defects at the interface of high-k dielectrics and compound semiconductors

As silicon based devices in integrated circuits reach the fundamental limits of dimensional scaling there is growing research interest in the use of high electron mobility channel materials, such as indium gallium arsenide (InGaAs), in conjunction with high dielectric constant (high-k) gate oxides, for Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) based devices. The motivation for employing high mobility channel materials is to reduce power dissipation in integrated circuits while also providing improved performance. One of the primary challenges to date in the field of III-V semiconductors has been the observation of high levels of defect densities at the high-k/III-V interface, which prevents surface inversion of the semiconductor. The work presented in this PhD thesis details the characterization of MOS devices incorporating high-k dielectrics on III-V semiconductors. The analysis examines the effect of modifying the semiconductor bandgap in MOS structures incorporating InxGa1-xAs (x: 0, 0.15. 0.3, 0.53) layers, the optimization of device passivation procedures designed to reduce interface defect densities, and analysis of such electrically active interface defect states for the high-k/InGaAs system. Devices are characterized primarily through capacitance-voltage (CV) and conductance-voltage (GV) measurements of MOS structures both as a function of frequency and temperature. In particular, the density of electrically active interface states was reduced to the level which allowed the observation of true surface inversion behavior in the In0.53Ga0.47As MOS system. This was achieved by developing an optimized (NH4)2S passivation, minimized air exposure, and atomic layer deposition of an Al2O3 gate oxide. An extraction of activation energies allows discrimination of the mechanisms responsible for the inversion response. Finally a new approach is described to determine the minority carrier generation lifetime and the oxide capacitance in MOS structures. The method is demonstrated for an In0.53Ga0.47As system, but is generally applicable to any MOS structure exhibiting a minority carrier response in inversion.

A tight-binding analysis of the electronic properties of III-nitride semiconductors

This thesis divides into two distinct parts, both of which are underpinned by the tight-binding model. The first part covers our implementation of the tight-binding model in conjunction with the Berry phase theory of electronic polarisation to probe the atomistic origins of spontaneous polarisation and piezoelectricity as well as attempting to accurately calculate the values and coefficients associated with these phenomena. We first develop an analytic model for the polarisation of a one-dimensional linear chain of atoms. We compare the zincblende and ideal wurtzite structures in terms of effective charges, spontaneous polarisation and piezoelectric coefficients, within a first nearest neighbour tight-binding model. We further compare these to real wurtzite structures and conclude that accurate quantitative results are beyond the scope of this model but qualitative trends can still be described. The second part of this thesis deals with implementing the tight-binding model to investigate the effect of local alloy fluctuations in bulk AlGaN alloys and InGaN quantum wells. We calculate the band gap evolution of Al1_xGaxN across the full composition range and compare it to experiment as well as fitting bowing parameters to the band gap as well as to the conduction band and valence band edges. We also investigate the wavefunction character of the valence band edge to determine the composition at which the optical polarisation switches in Al1_xGaxN alloys. Finally, we examine electron and hole localisation in InGaN quantum wells. We show how the built-in field localises the carriers along the c-axis and how local alloy fluctuations strongly localise the highest hole states in the c-plane, while the electrons remain delocalised in the c-plane. We show how this localisation affects the charge density overlap and also investigate the effect of well width fluctuations on the localisation of the electrons.

Piezo force microscopy and peakforce tuna measurements of III-V semiconductor nanowires

GaN, InP and GaAs nanowires were investigated for piezoelectric response. Nanowires and structures based on them can find wide applications in areas purposes such as nanogenarators, nanodrives, Solar cells and other perspective areas. Experemental measurements were carried out on AFM Bruker multimode 8 and data was handled with Nanoscope software. AFM techniques permitted not only to visualize the surface topography, but also to show distribution of piezoresponse and allowed to calculate its properties. The calculated values are in the same range as published by other authors.

Growth and characterization of III-V compound semiconductor nanostructures by metalorganic chemical vapor deposition

Planar <110> GaAs nanowires and quantum dots grown by atmospheric MOCVD have been introduced to non-standard growth conditions such as incorporating Zn and growing them on free-standing suspended films and on 10° off-cut substrates. Zn doped nanowires exhibited periodic notching along the axis of the wire that is dependent on Zn/Ga gas phase molar ratios. Planar nanowires grown on suspended thin films give insight into the mobility of the seed particle and change in growth direction. Nanowires that were grown on the off-cut sample exhibit anti-parallel growth direction changes. Quantum dots are grown on suspended thin films and show preferential growth at certain temperatures. Envisioned nanowire applications include twin-plane superlattices, axial pn-junctions, nanowire lasers, and the modulation of nanowire growth direction against an impeding barrier and varying substrate conditions.

Growth and application of planar III-V semiconductor nanowires grown with MOCVD

The semiconductor nanowire has been widely studied over the past decade and identified as a promising nanotechnology building block with application in photonics and electronics. The flexible bottom-up approach to nanowire growth allows for straightforward fabrication of complex 1D nanostructures with interesting optical, electrical, and mechanical properties. III-V nanowires in particular are useful because of their direct bandgap, high carrier mobility, and ability to form heterojunctions and have been used to make devices such as light-emitting diodes, lasers, and field-effect transistors. However, crystal defects are widely reported for III-V nanowires when grown in the common out-of-plane <111>B direction. Furthermore, commercialization of nanowires has been limited by the difficulty of assembling nanowires with predetermined position and alignment on a wafer-scale. In this thesis, planar III-V nanowires are introduced as a low-defect and integratable nanotechnology building block grown with metalorganic chemical vapor deposition. Planar GaAs nanowires grown with gold seed particles self-align along the <110> direction on the (001) GaAs substrate. Transmission electron microscopy reveals that planar GaAs nanowires are nearly free of crystal defects and grow laterally and epitaxially on the substrate surface. The nanowire morphology is shown to be primarily controlled through growth temperature and an ideal growth window of 470 +\- 10 °C is identified for planar GaAs nanowires. Extension of the planar growth mode to other materials is demonstrated through growth of planar InAs nanowires. Using a sacrificial layer, the transfer of planar GaAs nanowires onto silicon substrates with control over the alignment and position is presented. A metal-semiconductor field-effect transistor fabricated with a planar GaAs nanowire shows bulk-like low-field electron transport characteristics with high mobility. The aligned planar geometry and excellent material quality of planar III-V nanowires may lead to highly integrated III-V nanophotonics and nanoelectronics.

Growth and Characterization of III-V Semiconductor Materials for MOCVD Reactor Qualification and Process Control

Metalorganic chemical vapor deposition is examined as a technique for growing compound semiconductor structures. Material analysis techniques for characterizing the quality and properties of compound semiconductor material are explained and data from recent commissioning work on a newly installed reactor at the University of Illinois is presented.

A III-V channel field effect transistor for non-classical CMOS: process optimisation for improved gate stack function

This thesis describes a collection of studies into the electrical response of a III-V MOS stack comprising metal/GaGdO/GaAs layers as a function of fabrication process variables and the findings of those studies. As a result of this work, areas of improvement in the gate process module of a III-V heterostructure MOSFET were identified. Compared to traditional bulk silicon MOSFET design, one featuring a III-V channel heterostructure with a high-dielectric-constant oxide as the gate insulator provides numerous benefits, for example: the insulator can be made thicker for the same capacitance, the operating voltage can be made lower for the same current output, and improved output characteristics can be achieved without reducing the channel length further. It is known that transistors composed of III-V materials are most susceptible to damage induced by radiation and plasma processing. These devices utilise sub-10 nm gate dielectric films, which are prone to contamination, degradation and damage. Therefore, throughout the course of this work, process damage and contamination issues, as well as various techniques to mitigate or prevent those have been investigated through comparative studies of III-V MOS capacitors and transistors comprising various forms of metal gates, various thicknesses of GaGdO dielectric, and a number of GaAs-based semiconductor layer structures. Transistors which were fabricated before this work commenced, showed problems with threshold voltage control. Specifically, MOSFETs designed for normally-off (VTH > 0) operation exhibited below-zero threshold voltages. With the results obtained during this work, it was possible to gain an understanding of why the transistor threshold voltage shifts as the gate length decreases and of what pulls the threshold voltage downwards preventing normally-off device operation. Two main culprits for the negative VTH shift were found. The first was radiation damage induced by the gate metal deposition process, which can be prevented by slowing down the deposition rate. The second was the layer of gold added on top of platinum in the gate metal stack which reduces the effective work function of the whole gate due to its electronegativity properties. Since the device was designed for a platinum-only gate, this could explain the below zero VTH. This could be prevented either by using a platinum-only gate, or by matching the layer structure design and the actual gate metal used for the future devices. Post-metallisation thermal anneal was shown to mitigate both these effects. However, if post-metallisation annealing is used, care should be taken to ensure it is performed before the ohmic contacts are formed as the thermal treatment was shown to degrade the source/drain contacts. In addition, the programme of studies this thesis describes, also found that if the gate contact is deposited before the source/drain contacts, it causes a shift in threshold voltage towards negative values as the gate length decreases, because the ohmic contact anneal process affects the properties of the underlying material differently depending on whether it is covered with the gate metal or not. In terms of surface contamination; this work found that it causes device-to-device parameter variation, and a plasma clean is therefore essential. This work also demonstrated that the parasitic capacitances in the system, namely the contact periphery dependent gate-ohmic capacitance, plays a significant role in the total gate capacitance. This is true to such an extent that reducing the distance between the gate and the source/drain ohmic contacts in the device would help with shifting the threshold voltages closely towards the designed values. The findings made available by the collection of experiments performed for this work have two major applications. Firstly, these findings provide useful data in the study of the possible phenomena taking place inside the metal/GaGdO/GaAs layers and interfaces as the result of chemical processes applied to it. In addition, these findings allow recommendations as to how to best approach fabrication of devices utilising these layers.

The development of planar high-K/III-V p-channel MOSFETs for post-silicon CMOS

Conventional Si complementary-metal-oxide-semiconductor (CMOS) scaling is fast approaching its limits. The extension of the logic device roadmap for future enhancements in transistor performance requires non-Si materials and new device architectures. III-V materials, due to their superior electron transport properties, are well poised to replace Si as the channel material beyond the 10nm technology node to mitigate the performance loss of Si transistors from further reductions in supply voltage to minimise power dissipation in logic circuits. However several key challenges, including a high quality dielectric/III-V gate stack, a low-resistance source/drain (S/D) technology, heterointegration onto a Si platform and a viable III-V p-metal-oxide-semiconductor field-effect-transistor (MOSFET), need to be addressed before III-Vs can be employed in CMOS. This Thesis specifically addressed the development and demonstration of planar III-V p-MOSFETs, to complement the n-MOSFET, thereby enabling an all III-V CMOS technology to be realised. This work explored the application of InGaAs and InGaSb material systems as the channel, in conjunction with Al2O3/metal gate stacks, for p-MOSFET development based on the buried-channel flatband device architecture. The body of work undertaken comprised material development, process module development and integration into a robust fabrication flow for the demonstration of p-channel devices. The parameter space in the design of the device layer structure, based around the III-V channel/barrier material options of In_x≥0.53Ga_1-xAs/In_0.52Al_0.48As and In_x≥0.1Ga_1-xSb/AlSb, was systematically examined to improve hole channel transport. A mobility of 433 cm²/Vs, the highest room temperature hole mobility of any InGaAs quantum-well channel reported to date, was obtained for the In_0.85Ga_0.15As (2.1% strain) structure. S/D ohmic contacts were developed based on thermally annealed Au/Zn/Au metallisation and validated using transmission line model test structures. The effects of metallisation thickness, diffusion barriers and de-oxidation conditions were examined. Contacts to InGaSb-channel structures were found to be sensitive to de-oxidation conditions. A fabrication process, based on a lithographically-aligned double ohmic patterning approach, was realised for deep submicron gate-to-source/drain gap (L_side) scaling to minimise the access resistance, thereby mitigating the effects of parasitic S/D series resistance on transistor performance. The developed process yielded gaps as small as 20nm. For high-k integration on GaSb, ex-situ ammonium sulphide ((NH₄)₂S) treatments, in the range 1%-22%, for 10min at 295K were systematically explored for improving the electrical properties of the Al₂O₃/GaSb interface. Electrical and physical characterisation indicated the 1% treatment to be most effective with interface trap densities in the range of 4 - 10×10¹²cm^-2eV^-1 in the lower half of the bandgap. An extended study, comprising additional immersion times at each sulphide concentration, was further undertaken to determine the surface roughness and the etching nature of the treatments on GaSb. A number of p-MOSFETs based on III-V-channels with the most promising hole transport and integration of the developed process modules were successfully demonstrated in this work. Although the non-inverted InGaAs-channel devices showed good current modulation and switch-off characteristics, several aspects of performance were non-ideal; depletion-mode operation, modest drive current (I_d,sat=1.14mA/mm), double peaked transconductance (g_m=1.06mS/mm), high subthreshold swing (SS=301mV/dec) and high on-resistance (R_on=845kΩ.μm). Despite demonstrating substantial improvement in the on-state metrics of I_d,sat (11×), g_m (5.5×) and R_on (5.6×), inverted devices did not switch-off. Scaling gate-to-source/drain gap (L_side) from 1μm down to 70nm improved I_d,sat (72.4mA/mm) by a factor of 3.6 and gm (25.8mS/mm) by a factor of 4.1 in inverted InGaAs-channel devices. Well-controlled current modulation and good saturation behaviour was observed for InGaSb-channel devices. In the on-state In_0.3Ga_0.7Sb-channel (I_d,sat=49.4mA/mm, g_m=12.3mS/mm, R_on=31.7kΩ.μm) and In_0.4Ga_0.6Sb-channel (I_d,sat=38mA/mm, g_m=11.9mS/mm, R_on=73.5kΩ.μm) devices outperformed the InGaAs-channel devices. However the devices could not be switched off. These findings indicate that III-V p-MOSFETs based on InGaSb as opposed to InGaAs channels are more suited as the p-channel option for post-Si CMOS.

Design of Nanophotonic Antireflection Coatings for III-V Thin-Film Photovoltaics

Thin-film photovoltaics have provided a critical design avenue to help decrease the overall cost of solar power. However, a major drawback of thin-film solar cell technology is decreased optical absorption, making compact, high-quality antireflection coatings of critical importance to ensure that all available light enters the cell. In this thesis, we describe high efficiency thin-film InP and GaAs solar cells that utilize a periodic array of nanocylinders as antireflection coatings. We use coupled optical and electrical simulations to find that these nanophotonic structures reduce the solar-weighted average reflectivity of InP and GaAs solar cells to around 1.3 %, outperforming the best double-layer antireflection coatings. The coupling between Mie scattering resonances and thin-film interference effects accurately describes the optical enhancement provided by the nanocylinders. The spectrally resolved reflectivity and J-V characteristics of the devices under AM1.5G solar illumination are determined via the coupled optical and electrical simulations, resulting in predicted power conversion efficiencies > 23 %. We conclude that the nanostructured coatings reduce reflection without negatively affecting the electronic properties of the InP and GaAs solar cells by separating the nanostructured optical components from the active layer of the device.

Study of the influence of indium segregation on the optical properties of InGaAs/GaAs quantum wells via split-operator method

In the case of quantum wells, the indium segregation leads to complex potential profiles that are hardly considered in the majority of the theoretical models. The authors demonstrated that the split-operator method is useful tool for obtaining the electronic properties in these cases. Particularly, they studied the influence of the indium surface segregation in optical properties of InGaAs/GaAs quantum wells. Photoluminescence measurements were carried out for a set of InGaAs/GaAs quantum wells and compared to the results obtained theoretically via split-operator method, showing a good agreement.