Polynomial Coefficient Based Multi-Tone Testing of Analog Circuits

Abstract—A method of testing for parametric faults of analog circuits based on a polynomial representaion of fault-free function of the circuit is presented. The response of the circuit under test (CUT) is estimated as a polynomial in the applied input voltage at relevant frequencies apart from DC. Classification of CUT is based on a comparison of the estimated polynomial coefficients with those of the fault free circuit. The method needs very little augmentation of circuit to make it testable as only output parameters are used for classification. This procedure is shown to uncover several parametric faults causing smaller than 5 % deviations the nominal values. Fault diagnosis based upon sensitivity of polynomial coefficients at relevant frequencies is also proposed.

Bounds on Defect Level and Fault Coverage in Linear Analog Circuit Testing

Transfer function coefficients (TFC) are widely used to test linear analog circuits for parametric and catastrophic faults. This paper presents closed form expressions for an upper bound on the defect level (DL) and a lower bound on fault coverage (FC) achievable in TFC based test method. The computed bounds have been tested and validated on several benchmark circuits. Further, application of these bounds to scalable RC ladder networks reveal a number of interesting characteristics. The approach adopted here is general and can be extended to find bounds of DL and FC of other parametric test methods for linear and non-linear circuits.

V-Transform: “An Enhanced Polynomial Coefficient Based DC Test for Non-linear Analog Circuits

Abstract—DC testing of parametric faults in non-linear analog circuits based on a new transformation, entitled, V-Transform acting on polynomial coefficient expansion of the circuit function is presented. V-Transform serves the dual purpose of monotonizing polynomial coefficients of circuit function expansion and increasing the sensitivity of these coefficients to circuit parameters. The sensitivity of V-Transform Coefficients (VTC) to circuit parameters is up to 3x-5x more than sensitivity of polynomial coefficients. As a case study, we consider a benchmark elliptic filter to validate our method. The technique is shown to uncover hitherto untestable parametric faults whose sizes are smaller than 10 % of the nominal values. I.

Analog/RF Built-in-Self-Test Subsystem for a Mobile Broadcast Video Receiver in 65-nm CMOS

A built-in-self-test (BIST) subsystem embedded in a 65-nm mobile broadcast video receiver is described. The subsystem is designed to perform analog and RF measurements at multiple internal nodes of the receiver. It uses a distributed network of CMOS sensors and a low bandwidth, 12-bit A/D converter to perform the measurements with a serial bus interface enabling a digital transfer of measured data to automatic test equipment (ATE). A perturbation/correlation based BIST method is described, which makes pass/fail determination on parts, resulting in significant test time and cost reduction.

Extrinsic Analog Synthesis using Piecewise Linear Current-Mode Circuits

A methodology is presented for the synthesis of analog circuits using piecewise linear (PWL) approximations. The function to be synthesized is divided into PWL segments such that each segment can be realized using elementary MOS current-mode programmable-gain circuits. A number of these elementary current-mode circuits when connected in parallel, it is possible to realize piecewise linear approximation of any arbitrary analog function with in the allowed approximation error bounds. Simulation results show a close agreement between the desired function and the synthesized output. The number of PWL segments used for approximation and hence the circuit area is determined by the required accuracy and the smoothness of the resulting function.

A mostly-digital analog scan-out chain for low bandwidth voltage measurement for analog IP test

A method of precise measurement of on-chip analog voltages in a mostly-digital manner, with minimal overhead, is presented. A pair of clock signals is routed to the node of an analog voltage. This analog voltage controls the delay between this pair of clock signals, which is then measured in an all-digital manner using the technique of sub-sampling. This sub-sampling technique, having measurement time and accuracy trade-off, is well suited for low bandwidth signals. This concept is validated by designing delay cells, using current starved inverters in UMC 130nm CMOS process. Sub-mV accuracy is demonstrated for a measurement time of few seconds.

Towards formal verification of analog mixed signal designs using SPICE circuit simulation traces

An extension to a formal verification approach of hybrid systems is proposed to verify analog and mixed signal (AMS) designs. AMS designs can be formally modeled as hybrid systems and therefore lend themselves to the formal analysis and verification techniques applied to hybrid systems. The proposed approach employs simulation traces obtained from an actual design implementation of AMS circuit blocks (for example, in the form of SPICE netlists) to carry out formal analysis and verification. This enables the same platform used for formally validating an abstract model of an AMS design, to be also used for validating its different refinements and design implementation; thereby, providing a simple route to formal verification at different levels of implementation. The feasibility of the proposed approach is demonstrated with a case study based on a tunnel diode oscillator. Since the device characteristic of a tunnel diode is highly non-linear with a negative resistance region, dynamic behavior of circuits in which it is employed as an element is difficult to model, analyze and verify within a general hybrid system formal verification tool. In the case study presented the formal model and the proposed computational techniques have been incorporated into CheckMate, a formal verification tool based on MATLAB and Simulink-Stateflow Framework from MathWorks.

l-pGlu-(2-propyl)-l-His-l-ProNH2 attenuates 4-aminopyridine-induced epileptiform activity and sodium current: a possible action of new thyrotropin-releasing hormone analog for its anticonvulsant potential

L-PGlu-(2-proPyl)-L-His-L-ProNH(2) (NP-647) is a CNS active thyrotropin-releasing hormone (TRH) analog with potential application in various CNS disorders including seizures. In the present study, mechanism of action for protective effect of NP-647 was explored by studying role of NP-647 on epileptiform activity and sodium channels by using patch-clamp methods. Epileptiform activity was induced in subicular pyramidal neurons of hippocampal slice of rat by perfusing 4-aminopyridine (4-AP) containing Mg(+2)-free normal artificial cerebrospinal fluid (nACSF). Increase in mean firing frequency was observed after perfusion of 4-AP and zero Mg(+2) (2.10+/-0.47 Hz) as compared with nACSF (0.12+/-0.08 Hz). A significant decrease in mean firing frequency (0.61+/-0.22 Hz), mean frequency of epileptiform events (0.03+/-0.02 Hz vs. 0.22+/-0.05 Hz of 4-AP+0 Mg), and average number of action potentials in paroxysmal depolarization shift-burst (2.54+/-1.21 Hz vs. 8.16+/-0.88 Hz of 4-AP +0 Mg) was observed. A significant reduction in peak dV/dt (246+/-19 mV ms(-1) vs. 297 18 mV ms-1 of 4-AP+0 Mg) and increase (1.332+/-0.018 ms vs. 1.292+/-0.019 ms of 4-AP+0 Mg) in time required to reach maximum depolarization were observed indicating role of sodium channels. Concentration-dependent depression of sodium current was observed after exposure to dorsal root ganglion neurons to NP-647. NP-647 at different concentrations (1, 3, and 10 mu M) depressed sodium current (15+/-0.5%, 50+/-2.6%, and 75+/-0.7%, respectively). However, NP-647 did not show change in the peak sodium current in CNa18 cells. Results of present study demonstrated potential of NP-647 in the inhibition of epileptiform activity by inhibiting sodium channels indirectly. (C) 2011 IBRO. Published by Elsevier Ltd. All rights reserved.

Aza-heterocyclic ligand assisted assembly of new cobalt MOFs with pcu and graphite related structures

A hydrothermal reaction of a mixture of cobalt salt, 5-nitro isophthalic acid and triazole (compound I), 3-aminotriazole (3-AT) (compound II) and 3,5-diaminotriazole (compound III) at 220 degrees C for a day resulted in the isolation of three different, but related, compounds containing cobalt clusters. The three-dimensional compounds have Co-5 (compound-I) and Co-4 (compound-II and compound-III) clusters connected through the carboxylate and triazolate forming structures with pcu net (compound-I and compound-II) and a graphite-related net (compound-III). The water molecules (coordinated and lattice) can be readily re-adsorbed by the structure of compound-I, whereas the removal of the water molecule leads to a collapse of the structures of compound-II and compound-III. The TGA studies suggest the possibility of an intermediate structure for compound-1, which was investigated using in situ single crystal to single crystal (SCSC) transformations. The identification of an intermediate structure during the dehydration/hydration cycle in compound-I is important and provides important pointers about the dynamics of the water molecules in these compounds. Compound-I was also investigated in detail using a variety of spectroscopic techniques such as IR, UV-Vis spectroscopy etc. Magnetic studies on the synthesized compounds indicate anti-ferromagnetic behavior.

DNA Binding and Oxidative Cleavage Activity of Ternary (alpha-Lipoic Acid) Copper(II) Complex of Heterocyclic Base

Ternary copper(II) complex Cu(a-lipo)(phen)(Cl)](NO3) where a-lipo = a-lipoic acid, phen is N, N-donor heterocyclic base, 1,10-phenanthroline was synthesized, characterized, and its DNA binding and cleavage activity were studied. Binding interactions of the complex with calf thymus (CT) DNA has been investigated by emission, viscosity, and DNA melting studies. The complex shows efficient oxidative cleavage of SC-DNA in the presence of 3-mercaptopropionic acid involving hydroxyl radical species, and results of control experiments exhibit the inhibition of DNA cleavage in the presence of hydroxyl radical scavengers, viz. DMSO and KI.

Device oriented statistical modeling method for process variability in 45nm analog CMOS technology

With the rapid scaling down of the semiconductor process technology, the process variation aware circuit design has become essential today. Several statistical models have been proposed to deal with the process variation. We propose an accurate BSIM model for handling variability in 45nm CMOS technology. The MOSFET is designed to meet the specification of low standby power technology of International Technology Roadmap for Semiconductors (ITRS).The process parameters variation of annealing temperature, oxide thickness, halo dose and title angle of halo implant are considered for the model development. One parameter variation at a time is considered for developing the model. The model validation is done by performance matching with device simulation results and reported error is less than 10%.© (2012) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.

Time-Based All-Digital Technique for Analog Built-in Self-Test

A scheme for built-in self-test of analog signals with minimal area overhead for measuring on-chip voltages in an all-digital manner is presented. The method is well suited for a distributed architecture, where the routing of analog signals over long paths is minimized. A clock is routed serially to the sampling heads placed at the nodes of analog test voltages. This sampling head present at each test node, which consists of a pair of delay cells and a pair of flip-flops, locally converts the test voltage to a skew between a pair of subsampled signals, thus giving rise to as many subsampled signal pairs as the number of nodes. To measure a certain analog voltage, the corresponding subsampled signal pair is fed to a delay measurement unit to measure the skew between this pair. The concept is validated by designing a test chip in a UMC 130-nm CMOS process. Sub-millivolt accuracy for static signals is demonstrated for a measurement time of a few seconds, and an effective number of bits of 5.29 is demonstrated for low-bandwidth signals in the absence of sample-and-hold circuitry.