Effect of heavily doped boron on bandgap narrowing of strained SiGe layers

Taking into account the compensation effect of B to Ge in strained SiGe layers for the first time, the effect of heavily doped boron on the bandgap narrowing of strained SiGe layers is calculated, and the classical Jain-Roulston (J-R) model is modified. The results show that our modified J-R model well fits the experimental values. Based on the modified J-R model, the real bandgap narrowing distribution between the conduction and valence bands is further calculated, which has great influence on modelling the electrical characteristics of SiGe heterojunction bipolar transistors.

Study on Mg memory effect in npn type AlGaN/GaN HBT structures grown by MOCVD

AlGaN/GaN npn heterojunction bipolar transistor structures were grown by low-pressure MOCVD. Secondary ion mass spectroscopy (SIMS) measurements were carried out to study the Mg memory effect and redistribution in the emitter-base junction. The results indicated that there is a Mg-rich film formed in the ongrowing layer after the Cp2Mg source is switched off. The Mg-rich film can be confined in the base section by switching off the Cp2Mg source for appropriate time before the end of base growth. Low temperature growth of the undoped GaN spacer suppresses the Mg redistribution from Mg rich film. The delay rate of the Mg profile in sample C with spacer growing in low temperature is about 56 nm/decade, which becomes sharper than 80 nm/decade of the samples A and B without low temperature spacer. (C) 2005 Elsevier Ltd. All rights reserved.

High Temperature Characteristics of 3C-SiC/Si Heterojunction Diodes Grown by LPCVD

The high temperature (300～480K) characteristics of the n-3C-SiC/p-Si heterojunction diodes (HJD) fabricated by low-pressure chemical vapor deposition on Si (100) substrates are investigated.The obtained diode with best rectifying properties has 1.8×104 of ratio at room temperature,and slightly rectifying characteristics with 3.1 of rectification ratio is measured at 480K of an ambient temperature .220V of reverse breakdown voltage is acquired at 300K.Capacitance-voltage characteristics show that the abrupt junction model is applicable to the SiC/Si HJD structure and the built-in voltage is 0.75V.An ingenious equation is employed to perfectly simulate and explain the forward current density-voltage data measured at various temperatures.The 3C-SiC/Si HJD represents a promising approach for the fabrication of high quality heterojunction devices such as SiC-emitter heterojunction bipolar transistors.

Heteroepitaxial Growth and Heterojunction Characteristics of Voids-Free n-3C-SiC on p-Si(100)

Highly oriented voids-free 3C-SiC heteroepitaxial layers are grown on φ50mm Si (100) substrates by low pressure chemical vapor deposition (LPCVD). The initial stage of carbonization and the surface morphology of carbonization layers of Si(100) are studied using reflection high energy electron diffraction (RHEED) and scanning electron microscopy (SEM). It is shown that the optimized carbonization temperature for the growth of voids-free 3S-SiC on Si (100) substrates is 1100 ℃. The electrical properties of SiC layers are characterized using Van der Pauw method. The I-V, C-V, and the temperature dependence of I-V characteristics in n-3C-SiC-p-Si heterojunctions with AuGeNi and Al electrical pads are investigated. It is shown that the maximum reverse breakdown voltage of the n-3C-SiC-p-Si heterojunction diodes reaches to 220V at room temperature. These results indicate that the SiC/Si heterojunction diode can be used to fabricate the wide bandgap emitter SiC/Si heterojunction bipolar transistors (HBT's).

SiGe HBTs on Bonded SOI Incorporating Buried Silicide Layers

The performance of silicon bipolar transistors has been significantly improved by the use of ultra narrow base layers of SiGe. To further improve device performance by minimising parasitic resistance and capacitance the authors produced an unique silicon-on-insulator (SOI) substrate incorporating a buried tungsten disilicide layer. This structure forms the basis of a recent submission by Zarlink Semiconductors ( Silvaco, DeMontfort & Queen�s) to DTI for high voltage devices for automotive applications. The Queen�s part of the original EPSRC project was rated as tending to outstanding.

Improved Thermal Performance of SOI Using Compound Buried Layer

The buried oxide (BOX) layer in silicon on insulator (SOI) was replaced by a compound buried layer (CBL) containing layers of SiO2, polycrystalline silicon (polysilicon), and SiO2. The undoped polysilicon in the CBL acted as a dielectric with a higher thermal conductivity than SiO2. CBL provides a reduced thermal resistance with the same equivalent oxide thickness as a standard SiO2 buried layer. Thermal resistance was further reduced by lateral heat flow through the polysilicon. Reduction in thermal resistance by up to 68% was observed, dependent on polysilicon thickness. CBL SOI substrates were designed and manufactured to achieve a 40% reduction in thermal resistance compared with an 1.0-μm SiO2 BOX. Power bipolar transistors with an active silicon layer thickness of 13.5 μm manufactured on CBL SOI substrates showed a 5%-17% reduction in thermal resistance compared with the standard SOI. This reduction was dependent on transistor layout geometry. Between 65% and 90% of the heat flow from these power transistors is laterally through the thick active silicon layer. Analysis confirmed that CBL SOI provided a 40% reduction in the vertical path thermal resistance. Devices employing thinner active silicon layers will achieve the greater benefit from reduction in vertical path thermal resistance offered by CBL SOI.

Multiobjective design optimization of IGBT power modules considering power cycling and thermal cycling

Insulated-gate bipolar transistor (IGBT) power modules find widespread use in numerous power conversion applications where their reliability is of significant concern. Standard IGBT modules are fabricated for general-purpose applications while little has been designed for bespoke applications. However, conventional design of IGBTs can be improved by the multiobjective optimization technique. This paper proposes a novel design method to consider die-attachment solder failures induced by short power cycling and baseplate solder fatigue induced by the thermal cycling which are among major failure mechanisms of IGBTs. Thermal resistance is calculated analytically and the plastic work design is obtained with a high-fidelity finite-element model, which has been validated experimentally. The objective of minimizing the plastic work and constrain functions is formulated by the surrogate model. The nondominated sorting genetic algorithm-II is used to search for the Pareto-optimal solutions and the best design. The result of this combination generates an effective approach to optimize the physical structure of power electronic modules, taking account of historical environmental and operational conditions in the field.

In situ diagnostics and prognostics of solder fatigue in IGBT modules for electric vehicle drives

This paper proposes an in situ diagnostic and prognostic (D&P) technology to monitor the health condition of insulated gate bipolar transistors (IGBTs) used in EVs with a focus on the IGBTs' solder layer fatigue. IGBTs' thermal impedance and the junction temperature can be used as health indicators for through-life condition monitoring (CM) where the terminal characteristics are measured and the devices' internal temperature-sensitive parameters are employed as temperature sensors to estimate the junction temperature. An auxiliary power supply unit, which can be converted from the battery's 12-V dc supply, provides power to the in situ test circuits and CM data can be stored in the on-board data-logger for further offline analysis. The proposed method is experimentally validated on the developed test circuitry and also compared with finite-element thermoelectrical simulation. The test results from thermal cycling are also compared with acoustic microscope and thermal images. The developed circuitry is proved to be effective to detect solder fatigue while each IGBT in the converter can be examined sequentially during red-light stopping or services. The D&P circuitry can utilize existing on-board hardware and be embedded in the IGBT's gate drive unit.

A novel single-phase ZCS-PWM high-power-factor boost rectifier

This paper presents a novel single-phase high-power-factor (HPF) pulsewidth-modulated (PWM) boost rectifier featuring soft commutation of the active switches at zero current (ZC), It incorporates the most desirable properties of conventional PWM and soft-switching resonant techniques.The input current shaping is achieved with average current mode control and continuous inductor current mode.This new PWM converter provides ZC turn on and turn off of the active switches, and it is suitable for high-power applications employing insulated gate bipolar transistors (IGBT's),The principle of operation, the theoretical analysis, a design example, and experimental results from a laboratory prototype rated at 1600 W with 400-Vdc output voltage are presented. The measured efficiency and the power factor were 96.2% and 0.99%, respectively, with an input current total harmonic distortion (THD) equal to 3.94%, for an input voltage with THD equal to 3.8%, at rated load.

A novel voltage step-down/up ZCS-PWM Zeta converter

This paper presents an analysis of a novel pulse-width-modulated (PWM) voltage step-down/up Zeta converter, featuring zero-current-switching (ZCS) at the active switches. The applications in de to de and ac to de (rectifier) operation modes are used as examples to illustrate the performance of this new ZCS-PWM Zeta converter. Regarding to the new ZCS-PWM Zeta rectifier proposed, it should be noticed that the average-current mode control is used in order to obtain a structure with high power-factor (HPF) and low total harmonic distortion (THD) at the input current.Two active switches (main and auxiliary transistors), two diodes, two small resonant inductors and one small resonant capacitor compose the novel ZCS-PWM soft-commutation cell, used in these new ZCS-PWM Zeta converters. In this cell, the turn-on of the active switches occurs in zero-current (ZC) and their turn-off in zero-current and zero-voltage (ZCZV). For the diodes, their turn-on process occurs in zero-voltage (ZV) and their reverse-recovery effects over the active switches are negligible. These characteristics make this cell suitable for Insulated-Gate Bipolar Transistors (IGBTs) applications.The main advantages of these new Zeta converters, generated from the new soft-commutation cell proposed, are possibility of obtaining isolation (through their accumulation inductors), and high efficiency, at wide load range. In addition, for the rectifier application, a high power factor and low THD in the input current ran be obtained, in agreement with LEC 1000-3-2 standards.The principle of operation, the theoretical analysis and a design example for the new de to de Zeta converter operating in voltage step-down mode are presented. Experimental results are obtained from a test unit with 500W output power, 110V(dc) output voltage, 220V(dc) input voltage, operating at 50kHz switching frequency. The efficiency measured at rated toad is equal to 97.3%for this new Zeta converter.Finally, the new Zeta rectifier is analyzed, and experimental results from a test unit rated at 500W output power, 110V(dc) output voltage, 220V(rms) input voltage, and operating at 50kHz switching frequency, are presented. The measured efficiency is equal to 96.95%, the power-factor is equal to 0.98, and the input current THD is equal to 19.07%, for this new rectifier operating at rated load.

Novel zero-current-switching PWM converters

This paper presents a new family of pulsewidth-modulated (PWM) converters, featuring soft commutation of the semiconductors at zero current (ZC) in the transistors and zero voltage (ZV) in the rectifiers, Besides operating at constant frequency and with reduced commutation losses, these new converters have output characteristics similar to the hard-switching-PWM counterpart, which means that there is no circulating reactive energy that would cause large conduction losses, the new family of zero-current-switching (ZCS)-PWM converters is suitable for high-power applications using insulated gate bipolar transistors (IGBT's). The advantages of the new ZCS-PWM boast converter employing IGBT's, rated at 1.6 kW and operating at 20 kHz, are presented, This new ZCS operation can reduce the average total power dissipation in the semiconductors practically by half, when compared with the hard-switching method, This new ZCS-PWM boost converter is suitable for high-power applications using Ie;BT's in power-factor correction, the principle of operation, theoretical analysis, and experimental results of the new ZCS-PWM boost converter are provided in this paper to verify the performance of this new family of converters.

New family of zero-current-switching PWM converter

A new family of dc-to-dc pulse-width-modulated (PWM) converters is presented. These converters feature soft-commutation at zero-current (ZC) in the active switches. The new ZCS-PWM Boost and new ZCS-PWM Zeta converters, both based on the new ZCS-PWM soft-commutation cell proposed, are used as examples to illustrate the operation of the new family of converters.

Photodetection with gate-controlled lateral BJTs from standard CMOS technology

The silicon-based gate-controlled lateral bipolar junction transistor (BJT) is a controllable four-terminal photodetector with very high responsivity at low-light intensities. It is a hybrid device composed of a MOSFET, a lateral BJT, and a vertical BJT. Using sufficient gate bias to operate the MOS transistor in inversion mode, the photodetector allows for increasing the photocurrent gain by 106 at low light intensities when the base-emitter voltage is smaller than 0.4 V, and BJT is off. Two operation modes, with constant voltage bias between gate and emitter/source terminals and between gate and base/body terminals, allow for tuning the photoresponse from sublinear to slightly above linear, satisfying the application requirements for wide dynamic range, high-contrast, or linear imaging. MOSFETs from a standard 0.18-μm triple-well complementary-metal oxide semiconductor technology with a width to length ratio of 8 μm /2 μm and a total area of ∼ 500μm2 are used. When using this area, the responsivities are 16-20 kA/W. © 2001-2012 IEEE.

Micro-inverter for integrated grid-tie photovoltaic module using resonant controller

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

A radial basis function network (RBFN) for function approximation

A radial basis function network (RBFN) circuit for function approximation is presented. Simulation and experimental results show that the network has good approximation capabilities. The RBFN was a squared hyperbolic secant with three adjustable parameters amplitude, width and center. To test the network a sinusoidal and sine function,vas approximated.