An Approach for Distance Relay Co-ordination using Support Vector Machines

In this paper, an approach to enhance the Extra High Voltage (EHV) Transmission system distance protection is presented. The scheme depends on the apparent impedance seen by the distance relay during the disturbance. In a distance relay,the impedance seen at the relay location is calculated from the fundamental frequency component of the voltage and current signals. Support Vector Machines (SVMs) are a new learning-byexample are employed in discriminating zone settings (Zone-1,Zone-2 and Zone-3) using the signals to be used by the relay.Studies on 265-bus system, an equivalent of practical Indian Western grid are presented for illustrating the proposed scheme.

An Investigation into the Dependence of the Arc Voltage on the Parameters of the Short-Circuit Current and the Design of the Vacuum Interrupter

The vacuum interrupter is extensively employed in the medium voltage switchgear for the interruption of the short-circuit current. The voltage across the arc during current interruption is termed as the arc voltage. The nature and magnitude of this arc voltage is indicative of the performance of the contacts and the vacuum interrupter as a whole. Also, the arc voltage depends on the parameters like the magnitude of short-circuit current, the arcing time, the point of opening of the contacts, the geometry and area of the contacts and the type of magnetic field. This paper investigates the dependency of the arc voltage on some of these parameters. The paper also discusses the usefulness of the arc voltage in diagnosing the performance of the contacts.

Energy Reduction in SRAM using Dynamic Voltage and Frequency Management

This paper describes a dynamic voltage frequency control scheme for a 256 X 64 SRAM block for reducing the energy in active mode and stand-by mode. The DVFM control system monitors the external clock and changes the supply voltage and the body bias so as to achieve a significant reduction in energy. The behavioral model of the proposed DVFM control system algorithm is described and simulated in HDL using delay and energy parameters obtained through SPICE simulation. The frequency range dictated by an external controller is 100 MHz to I GHz. The supply voltage of the complete memory system is varied in steps of 50 mV over the range of 500 mV to IV. The threshold voltage range of operation is plusmn100 mV around the nominal value, achieving 83.4% energy reduction in the active mode and 86.7% in the stand-by mode. This paper also proposes a energy replica that is used in the energy monitor subsystem of the DVFM system.

Compiler-Directed Frequency and Voltage Scaling for a Multiple Clock Domain

Multiple Clock Domain processors provide an attractive solution to the increasingly challenging problems of clock distribution and power dissipation. They allow their chips to be partitioned into different clock domains, and each domain’s frequency (voltage) to be independently configured. This flexibility adds new dimensions to the Dynamic Voltage and Frequency Scaling problem, while providing better scope for saving energy and meeting performance demands. In this paper, we propose a compiler directed approach for MCD-DVFS. We build a formal petri net based program performance model, parameterized by settings of microarchitectural components and resource configurations, and integrate it with our compiler passes for frequency selection.Our model estimates the performance impact of a frequency setting, unlike the existing best techniques which rely on weaker indicators of domain performance such as queue occupancies(used by online methods) and slack manifestation for a particular frequency setting (software based methods).We evaluate our method with subsets of SPECFP2000,Mediabench and Mibench benchmarks. Our mean energy savings is 60.39% (versus 33.91% of the best software technique)in a memory constrained system for cache miss dominated benchmarks, and we meet the performance demands.Our ED2 improves by 22.11% (versus 18.34%) for other benchmarks. For a CPU with restricted frequency settings, our energy consumption is within 4.69% of the optimal.

Dark Matter Halo Properties as Deduced from the Observed H I Scale Height Data, in The Low-Frequency Radio Universe

We use the HΙ scale height data along with the HΙ rotation curve as constraints to probe the shape and density profile of the dark matter halos of M31 (Andromeda) and the superthin, low surface brightness (LSB) galaxy UGC 07321. We model the galaxy as a two component system of gravitationally-coupled stars and gas subjected to the force field of a dark matter halo. For M31, we get a flattened halo which is required to match the outer galactic HΙ scale height data, with our best-fit axis ratio (0.4) lying at the most oblate end of the distributions obtained from cosmological simulations. For UGC 07321, our best-fit halo core radius is only slightly larger than the stellar disc scale length, indicating that the halo is important even at small radii in this LSB galaxy. The high value of the gas velocity dispersion required to match the scale height data can explain the low star-formation rate of this galaxy.

Bounds on Defect Level and Fault Coverage in Linear Analog Circuit Testing

Transfer function coefficients (TFC) are widely used to test linear analog circuits for parametric and catastrophic faults. This paper presents closed form expressions for an upper bound on the defect level (DL) and a lower bound on fault coverage (FC) achievable in TFC based test method. The computed bounds have been tested and validated on several benchmark circuits. Further, application of these bounds to scalable RC ladder networks reveal a number of interesting characteristics. The approach adopted here is general and can be extended to find bounds of DL and FC of other parametric test methods for linear and non-linear circuits.

An improved sapce phasor based current hysteresis controller with reduced switching frequency variations using variable parabolic bands

A current error space phasor based simple hysteresis controller is proposed in this paper to control the switching frequency variation in two-level pulsewidth-modulation (PWM) inverter-fed induction motor (IM) drives. A parabolic boundary for the current error space phasor is suggested for the first time to obtain the switching frequency spectrum for output voltage with hysteresis controller similar to the constant switching frequency voltage-controlled space vector PWM-based IM drive. A novel concept of online variation of this parabolic boundary, which depends on the operating speed of motor, is presented. A generalized technique that determines the set of unique parabolic boundaries for a two-level inverter feeding any given induction motor is described. The sector change logic is self-adaptive and is capable of taking the drive up to the six-step mode if needed. Steady-state and transient performance of proposed controller is experimentally verified on a 3.7-kW IM drive in the entire speed range. Close resemblance of the simulation and experimental results is shown.

Multicode STBC in Frequency-Selective Fading

Multicode operation in space-time block coded (STBC) multiple input multiple output (MIMO) systems can provide additional degrees of freedom in code domain to achieve high data rates. In such multicode STBC systems, the receiver experiences code domain interference (CDI) in frequency selective fading. In this paper, we propose a linear parallel interference cancellation (LPIC) approach to cancel the CDI in multicode STBC signals in frequency selective fading. The proposed detector first performs LPIC followed by STBC decoding. We present an SINK for the proposed detector. We evaluate the bit error rate (BER) performance of the system, and show that the proposed detector effectively cancels the CDI and achieves improved error performance. Our BER results further illustrate how the combined effect of interference cancellation, transmit diversity, and RAKE diversity affects the performance of the system.

INTACTE: An Interconnect Area, Delay, and Energy Estimation Tool for Microarchitectural Explorations

Prior work on modeling interconnects has focused on optimizing the wire and repeater design for trading off energy and delay, and is largely based on low level circuit parameters. Hence these models are hard to use directly to make high level microarchitectural trade-offs in the initial exploration phase of a design. In this paper, we propose INTACTE, a tool that can be used by architects toget reasonably accurate interconnect area, delay, and power estimates based on a few architecture level parameters for the interconnect such as length, width (in number of bits), frequency, and latency for a specified technology and voltage. The tool uses well known models of interconnect delay and energy taking into account the wire pitch, repeater size, and spacing for a range of voltages and technologies.It then solves an optimization problem of finding the lowest energy interconnect design in terms of the low level circuit parameters, which meets the architectural constraintsgiven as inputs. In addition, the tool also provides the area, energy, and delay for a range of supply voltages and degrees of pipelining, which can be used for micro-architectural exploration of a chip. The delay and energy models used by the tool have been validated against low level circuit simulations. We discuss several potential applications of the tool and present an example of optimizing interconnect design in the context of clustered VLIW architectures. Copyright 2007 ACM.