Integral energy performance characterization of semi-transparent photovoltaic elements for building integration under real operation conditions

In this paper, a methodology for the integral energy performance characterization (thermal, daylighting and electrical behavior) of semi-transparent photovoltaic modules (STPV) under real operation conditions is presented. An outdoor testing facility to analyze simultaneously thermal, luminous and electrical performance of the devices has been designed, constructed and validated. The system, composed of three independent measurement subsystems, has been operated in Madrid with four prototypes of a-Si STPV modules, each one corresponding to a specific degree of transparency. The extensive experimental campaign, continued for a whole year rotating the modules under test, has validated the reliability of the testing facility under varying environmental conditions. The thermal analyses show that both the solar protection and insulating properties of the laminated prototypes are lower than those achieved by a reference glazing whose characteristics are in accordance with the Spanish Technical Building Code. Daylighting analysis shows that STPV elements have an important lighting energy saving potential that could be exploited through their integration with strategies focused to reduce illuminance values in sunny conditions. Finally, the electrical tests show that the degree of transparency is not the most determining factor that affects the conversion efficiency.

Student academic performance stochastic simulator based on the Monte Carlo method

In this paper, a computer-based tool is developed to analyze student performance along a given curriculum. The proposed software makes use of historical data to compute passing/failing probabilities and simulates future student academic performance based on stochastic programming methods (MonteCarlo) according to the specific university regulations. This allows to compute the academic performance rates for the specific subjects of the curriculum for each semester, as well as the overall rates (the set of subjects in the semester), which are the efficiency rate and the success rate. Additionally, we compute the rates for the Bachelors degree, which are the graduation rate measured as the percentage of students who finish as scheduled or taking an extra year and the efficiency rate (measured as the percentage of credits of the curriculum with respect to the credits really taken). In Spain, these metrics have been defined by the National Quality Evaluation and Accreditation Agency (ANECA). Moreover, the sensitivity of the performance metrics to some of the parameters of the simulator is analyzed using statistical tools (Design of Experiments). The simulator has been adapted to the curriculum characteristics of the Bachelor in Engineering Technologies at the Technical University of Madrid(UPM).

Leakage-aware cooling management for improving server energy efficiency

The computational and cooling power demands of enterprise servers are increasing at an unsustainable rate. Understanding the relationship between computational power, temperature, leakage, and cooling power is crucial to enable energy-efficient operation at the server and data center levels. This paper develops empirical models to estimate the contributions of static and dynamic power consumption in enterprise servers for a wide range of workloads, and analyzes the interactions between temperature, leakage, and cooling power for various workload allocation policies. We propose a cooling management policy that minimizes the server energy consumption by setting the optimum fan speed during runtime. Our experimental results on a presently shipping enterprise server demonstrate that including leakage awareness in workload and cooling management provides additional energy savings without any impact on performance.

Energy and Lighting Performance of Buildings in the Neighbourhood Ciudad de los Angeles, Before and After Refurbishing.

The Spanish Ministry of Economy and Competitiveness is funding the SHERIF Research Project, which falls under the INNPACTO pr ogram. This project aims to increase the rate of the existing building refurbishment fro m the energy efficiency point of view by designing a facade system that must be an economica l, flexible and integrated solution 1 . Under this project has been performing several task s regarding the constructive characterization and energy evaluation of the therm al behaviour of facades on existing buildings . In order to perform the latter task, in which this article will focus, has been developing a survey of various buildings in the nei ghbourhood Ciudad de los Angeles, which has as main objective the comparison between the ac tual energy and light behaviour of different buildings, prior and posterior to any ref urbishment works have been undertaken. The evaluation of the actual performance of buildin gs before and after being refurbished is aimed to determine the impact of the work developed as well as learn from the work performed for future interventions.

Emergency management in the highways of the future. A performance-based multilayered ITS architecture design proposal

Emergency management is one of the key aspects within the day-to-day operation procedures in a highway. Efficiency in the overall response in case of an incident is paramount in reducing the consequences of any incident. However, the approach of highway operators to the issue of incident management is still usually far from a systematic, standardized way. This paper attempts to address the issue and provide several hints on why this happens, and a proposal on how the situation could be overcome. An introduction to a performance based approach to a general system specification will be described, and then applied to a particular road emergency management task. A real testbed has been implemented to show the validity of the proposed approach. Ad-hoc sensors (one camera and one laser scanner) were efficiently deployed to acquire data, and advanced fusion techniques applied at the processing stage to reach the specific user requirements in terms of functionality, flexibility and accuracy.

Power Converter Topologies for a High Performance Transformer Rectifier Unit in Aircraft Applications

This paper presents some power converter architectures and circuit topologies, which can be used to achieve the requirements of the high performance transformer rectifier unit in aircraft applications, mainly as: high power factor with low THD, high efficiency and high power density. The voltage and the power levels demanded for this application are: three-phase line-to-neutral input voltage of 115 or 230V AC rms (360 – 800Hz), output voltage of 28V DC or 270V DC(new grid value) and the output power up to tens of kilowatts.

Magnetic Attitude Control System for a Small Satellite. Impact on the Thermal Performance

El principal objetivo de la tesis es estudiar el acoplamiento entre los subsistemas de control de actitud y de control térmico de un pequeño satélite, con el fin de buscar la solución a los problemas relacionados con la determinación de los parámetros de diseño. Se considera la evolución de la actitud y de las temperaturas del satélite bajo la influencia de dos estrategias de orientación diferentes: 1) estabilización magnética pasiva de la orientación (PMAS, passive magnetic attitude stabilization), y 2) control de actitud magnético activo (AMAC, active magnetic attitude control). En primer lugar se presenta el modelo matemático del problema, que incluye la dinámica rotacional y el modelo térmico. En el problema térmico se considera un satélite cúbico modelizado por medio de siete nodos (seis externos y uno interno) aplicando la ecuación del balance térmico. Una vez establecido el modelo matemático del problema, se estudia la evolución que corresponde a las dos estrategias mencionadas. La estrategia PMAS se ha seleccionado por su simplicidad, fiabilidad, bajo coste, ahorrando consumo de potencia, masa coste y complejidad, comparado con otras estrategias. Se ha considerado otra estrategia de control que consigue que el satélite gire a una velocidad requerida alrededor de un eje deseado de giro, pudiendo controlar su dirección en un sistema inercial de referencia, ya que frecuentemente el subsistema térmico establece requisitos de giro alrededor de un eje del satélite orientado en una dirección perpendicular a la radiación solar incidente. En relación con el problema térmico, para estudiar la influencia de la velocidad de giro en la evolución de las temperaturas en diversos puntos del satélite, se ha empleado un modelo térmico linealizado, obtenido a partir de la formulación no lineal aplicando un método de perturbaciones. El resultado del estudio muestra que el tiempo de estabilización de la temperatura y la influencia de las cargas periódicas externas disminuye cuando aumenta la velocidad de giro. Los cambios de temperatura se reducen hasta ser muy pequeños para velocidades de rotación altas. En relación con la estrategia PMAC se ha observado que a pesar de su uso extendido entre los micro y nano satélites todavía presenta problemas que resolver. Estos problemas están relacionados con el dimensionamiento de los parámetros del sistema y la predicción del funcionamiento en órbita. Los problemas aparecen debido a la dificultad en la determinación de las características magnéticas de los cuerpos ferromagnéticos (varillas de histéresis) que se utilizan como amortiguadores de oscilaciones en los satélites. Para estudiar este problema se presenta un modelo analítico que permite estimar la eficiencia del amortiguamiento, y que se ha aplicado al estudio del comportamiento en vuelo de varios satélites, y que se ha empleado para comparar los resultados del modelo con los obtenidos en vuelo, observándose que el modelo permite explicar satisfactoriamente el comportamiento registrado. ABSTRACT The main objective of this thesis is to study the coupling between the attitude control and thermal control subsystems of a small satellite, and address the solution to some existing issues concerning the determination of their parameters. Through the thesis the attitude and temperature evolution of the satellite is studied under the influence of two independent attitude stabilization and control strategies: (1) passive magnetic attitude stabilization (PMAS), and (2) active magnetic attitude control (AMAC). In this regard the mathematical model of the problem is explained and presented. The mathematical model includes both the rotational dynamics and the thermal model. The thermal model is derived for a cubic satellite by solving the heat balance equation for 6 external and 1 internal nodes. Once established the mathematical model of the problem, the above mentioned attitude strategies were applied to the system and the temperature evolution of the 7 nodes of the satellite was studied. The PMAS technique has been selected to be studied due to its prevalent use, simplicity, reliability, and cost, as this strategy significantly saves the overall power, weight, cost, and reduces the complexity of the system compared to other attitude control strategies. In addition to that, another control law that provides the satellite with a desired spin rate along a desired axis of the satellite, whose direction can be controlled with respect to the inertial reference frame is considered, as the thermal subsystem of a satellite usually demands a spin requirement around an axis of the satellite which is positioned perpendicular to the direction of the coming solar radiation. Concerning the thermal problem, to study the influence of spin rate on temperature evolution of the satellite a linear approach of the thermal model is used, which is based on perturbation theory applied to the nonlinear differential equations of the thermal model of a spacecraft moving in a closed orbit. The results of this study showed that the temperature stabilization time and the periodic influence of the external thermal loads decreases by increasing the spin rate. However, the changes become insignificant for higher values of spin rate. Concerning the PMAS strategy, it was observed that in spite of its extended application to micro and nano satellites, still there are some issues to be solved regarding this strategy. These issues are related to the sizing of its system parameters and predicting the in-orbit performance. The problems were found to be rooted in the difficulties that exist in determining the magnetic characteristics of the ferromagnetic bodies (hysteresis rods) that are applied as damping devices on-board satellites. To address these issues an analytic model for estimating their damping efficiency is proposed and applied to several existing satellites in order to compare the results with their respective in-flight data. This model can explain the behavior showed by these satellites.

Rate-Adaptive LDPC-based key reconciliation for high performance quantum key distribution

The postprocessing or secret-key distillation process in quantum key distribution (QKD) mainly involves two well-known procedures: information reconciliation and privacy amplification. Information or key reconciliation has been customarily studied in terms of efficiency. During this, some information needs to be disclosed for reconciling discrepancies in the exchanged keys. The leakage of information is lower bounded by a theoretical limit, and is usually parameterized by the reconciliation efficiency (or inefficiency), i.e. the ratio of additional information disclosed over the Shannon limit. Most techniques for reconciling errors in QKD try to optimize this parameter. For instance, the well-known Cascade (probably the most widely used procedure for reconciling errors in QKD) was recently shown to have an average efficiency of 1.05 at the cost of a high interactivity (number of exchanged messages). Modern coding techniques, such as rate-adaptive low-density parity-check (LDPC) codes were also shown to achieve similar efficiency values exchanging only one message, or even better values with few interactivity and shorter block-length codes.

Establishing Quercus ilex under Mediterranean dry conditions: sowing recalcitrant acorns versus planting seedlings at different depths and tube shelter light transmissions

Article New Forests November 2015, Volume 46, Issue 5, pp 869-883 First online: 17 June 2015 Establishing Quercus ilex under Mediterranean dry conditions: sowing recalcitrant acorns versus planting seedlings at different depths and tube shelter light transmissionsJuan A. OlietAffiliated withDepartamento de Sistemas y Recursos Naturales, E.T.S. Ingenieros de Montes, Universidad Politécnica de Madrid Email author View author's OrcID profile , Alberto Vázquez de CastroAffiliated withDepartamento de Sistemas y Recursos Naturales, E.T.S. Ingenieros de Montes, Universidad Politécnica de Madrid, Jaime PuértolasAffiliated withLancaster Environment Centre, Lancaster University $39.95 / €34.95 / £29.95 * Rent the article at a discount Rent now * Final gross prices may vary according to local VAT. Get Access AbstractSuccess of Mediterranean dry areas restoration with oaks is a challenging goal. Testing eco-techniques that mimic beneficial effects of natural structures and ameliorate stress contributes to positive solutions to overcoming establishment barriers. We ran a factorial experiment in a dry area, testing two levels of solid wall transmission of tube shelters (60 and 80 %) plus a control mesh, and two depths (shallow and 15 cm depth) of placing either planted seedlings or acorns of Quercus ilex. Microclimate of the planting or sowing spots was characterized by measuring photosynthetically active radiation, temperature and relative humidity. Plant response was evaluated in terms of survival, phenology, acorn emergence and photochemical efficiency (measured through chlorophyll fluorescence). We hypothesize that tube shelters and deep planting improve Q. ilex post-planting and sowing performance because of the combined effects of reducing excessive radiation and improving access to moist soil horizons. Results show that temperature and PAR was reduced, and relative humidity increased, in deep spots. Midsummer photochemical efficiency indicates highest level of stress for oaks in 80 % light transmission shelter. Optimum acorn emergence in spring was registered within solid wall tree shelters, and maximum summer survival of germinants and of planted seedlings occurred when acorns or seedlings were placed at 15 cm depth irrespectively of light transmission of shelter. Survival of germinants was similar to that of planted seedlings. The importance of techniques to keep high levels of viability after sowing recalcitrant seeds in the field is emphasized in the study

Productive performance of brown-egg laying pullets from hatching to 5 weeks of age as affected by fiber inclusion, feed form, and energy concentration of the diet

The effects of fiber inclusion, feed form, and energy concentration of the diet on the growth performance of pullets from hatching to 5 wk age were studied in 2 experiments. In Experiment 1, there was a control diet based on cereals and soybean meal, and 6 extra diets that included 2 or 4% of cereal straw, sugar beet pulp (SBP), or sunflower hulls (SFHs) at the expense (wt/wt) of the whole control diet. From hatching to 5 wk age fiber inclusion increased (P < 0.05) ADG and ADFI, and improved (P < 0.05) energy efficiency (EnE; kcal AMEn/g ADG), but body weight (BW) uniformity was not affected. Pullets fed SFH tended to have higher ADG than pullets fed SBP (P = 0.072) with pullets fed straw being intermediate. The feed conversion ratio (FCR) was better (P < 0.05) with 2% than with 4% fiber inclusion. In Experiment 2, 10 diets were arranged as a 2×5 factorial with 2 feed forms (mash vs. crumbles) and 5 levels of AMEn (2,850, 2,900, 2,950, 3,000, and 3,050 kcal/kg). Pullets fed crumbles were heavier and had better FCR than pullets fed mash (P < 0.001). An increase in the energy content of the crumble diets reduced ADFI and improved FCR linearly, but no effects were detected with the mash diets (P < 0.01 and P < 0.05 for the interactions). Feeding crumbles tended to improve BW uniformity at 5 wk age (P = 0.077) but no effects were detected with increases in energy concentration of the diet. In summary, the inclusion of moderate amounts of fiber in the diet improves pullet performance from hatching to 5 wk age. The response of pullets to increases in energy content of the diet depends on feed form with a decrease in feed intake when fed crumbles but no changes when fed mash. Feeding crumbles might be preferred to feeding mash in pullets from hatching to 5 wk age.

Night time performance of a storage integrated solar thermophotovoltaic (SISTPV) system

Energy storage at low maintenance cost is one of the key challenges for generating electricity from the solar energy. This paper presents the theoretical analysis (verified by CFD) of the night time performance of a recently proposed conceptual system that integrates thermal storage (via phase change materials) and thermophotovoltaics for power generation. These storage integrated solar thermophotovoltaic (SISTPV) systems are attractive owing to their simple design (no moving parts) and modularity compared to conventional Concentrated Solar Power (CSP) technologies. Importantly, the ability of high temperature operation of these systems allows the use of silicon (melting point of 1680 K) as the phase change material (PCM). Silicon's very high latent heat of fusion of 1800 kJ/kg and low cost ($1.70/kg), makes it an ideal heat storage medium enabling for an extremely high storage energy density and low weight modular systems. In this paper, the night time operation of the SISTPV system optimised for steady state is analysed. The results indicate that for any given PCM length, a combination of small taper ratio and large inlet hole-to-absorber area ratio are essential to increase the operation time and the average power produced during the night time. Additionally, the overall results show that there is a trade-off between running time and the average power produced during the night time. Average night time power densities as high as 30 W/cm(2) are possible if the system is designed with a small PCM length (10 cm) to operate just a few hours after sun-set, but running times longer than 72 h (3 days) are possible for larger lengths (50 cm) at the expense of a lower average power density of about 14 W/cm(2). In both cases the steady state system efficiency has been predicted to be about 30%. This makes SISTPV systems to be a versatile solution that can be adapted for operation in a broad range of locations with different climate conditions, even being used off-grid and in space applications.

Performance variability in basketball players with intellectual impairment: Ankara World Championships 2013 analysis

The aim of the present study was to identify performance variability in basketball for players with intellectual impairment (II) and to compare it with able-bodied (AB) players. Official game statistics from the 13 games played in the Ankara World II-Basketball Championships (2013) were gathered and descriptive data, variability coefficient (VC), maximum scores and its Z-score were calculated from those players who participated at least 10 minutes per game (N = 46; guards = 10, forwards = 21, centers = 15). Results indicated higher performance variability and lower efficiency in shooting percentages and turnovers in II-players comparing with studies in ABplayers. Differences found between game positions indicated similar roles of guards, forwards and centers in II and AB-players. These findings are relevant to understand how II impact on basketball performance, which is a necessary step to develop specific eligibility systems in II-basketball according to the guidelines of the International Paralympic Committee.

Run-Time Dynamically-Adaptable FPGA-Based Architecture for High-Performance Autonomous Distributed Systems

Esta tesis doctoral se enmarca dentro del campo de los sistemas embebidos reconfigurables, redes de sensores inalámbricas para aplicaciones de altas prestaciones, y computación distribuida. El documento se centra en el estudio de alternativas de procesamiento para sistemas embebidos autónomos distribuidos de altas prestaciones (por sus siglas en inglés, High-Performance Autonomous Distributed Systems (HPADS)), así como su evolución hacia el procesamiento de alta resolución. El estudio se ha llevado a cabo tanto a nivel de plataforma como a nivel de las arquitecturas de procesamiento dentro de la plataforma con el objetivo de optimizar aspectos tan relevantes como la eficiencia energética, la capacidad de cómputo y la tolerancia a fallos del sistema. Los HPADS son sistemas realimentados, normalmente formados por elementos distribuidos conectados o no en red, con cierta capacidad de adaptación, y con inteligencia suficiente para llevar a cabo labores de prognosis y/o autoevaluación. Esta clase de sistemas suele formar parte de sistemas más complejos llamados sistemas ciber-físicos (por sus siglas en inglés, Cyber-Physical Systems (CPSs)). Los CPSs cubren un espectro enorme de aplicaciones, yendo desde aplicaciones médicas, fabricación, o aplicaciones aeroespaciales, entre otras muchas. Para el diseño de este tipo de sistemas, aspectos tales como la confiabilidad, la definición de modelos de computación, o el uso de metodologías y/o herramientas que faciliten el incremento de la escalabilidad y de la gestión de la complejidad, son fundamentales. La primera parte de esta tesis doctoral se centra en el estudio de aquellas plataformas existentes en el estado del arte que por sus características pueden ser aplicables en el campo de los CPSs, así como en la propuesta de un nuevo diseño de plataforma de altas prestaciones que se ajuste mejor a los nuevos y más exigentes requisitos de las nuevas aplicaciones. Esta primera parte incluye descripción, implementación y validación de la plataforma propuesta, así como conclusiones sobre su usabilidad y sus limitaciones. Los principales objetivos para el diseño de la plataforma propuesta se enumeran a continuación: • Estudiar la viabilidad del uso de una FPGA basada en RAM como principal procesador de la plataforma en cuanto a consumo energético y capacidad de cómputo. • Propuesta de técnicas de gestión del consumo de energía en cada etapa del perfil de trabajo de la plataforma. •Propuestas para la inclusión de reconfiguración dinámica y parcial de la FPGA (por sus siglas en inglés, Dynamic Partial Reconfiguration (DPR)) de forma que sea posible cambiar ciertas partes del sistema en tiempo de ejecución y sin necesidad de interrumpir al resto de las partes. Evaluar su aplicabilidad en el caso de HPADS. Las nuevas aplicaciones y nuevos escenarios a los que se enfrentan los CPSs, imponen nuevos requisitos en cuanto al ancho de banda necesario para el procesamiento de los datos, así como en la adquisición y comunicación de los mismos, además de un claro incremento en la complejidad de los algoritmos empleados. Para poder cumplir con estos nuevos requisitos, las plataformas están migrando desde sistemas tradicionales uni-procesador de 8 bits, a sistemas híbridos hardware-software que incluyen varios procesadores, o varios procesadores y lógica programable. Entre estas nuevas arquitecturas, las FPGAs y los sistemas en chip (por sus siglas en inglés, System on Chip (SoC)) que incluyen procesadores embebidos y lógica programable, proporcionan soluciones con muy buenos resultados en cuanto a consumo energético, precio, capacidad de cómputo y flexibilidad. Estos buenos resultados son aún mejores cuando las aplicaciones tienen altos requisitos de cómputo y cuando las condiciones de trabajo son muy susceptibles de cambiar en tiempo real. La plataforma propuesta en esta tesis doctoral se ha denominado HiReCookie. La arquitectura incluye una FPGA basada en RAM como único procesador, así como un diseño compatible con la plataforma para redes de sensores inalámbricas desarrollada en el Centro de Electrónica Industrial de la Universidad Politécnica de Madrid (CEI-UPM) conocida como Cookies. Esta FPGA, modelo Spartan-6 LX150, era, en el momento de inicio de este trabajo, la mejor opción en cuanto a consumo y cantidad de recursos integrados, cuando además, permite el uso de reconfiguración dinámica y parcial. Es importante resaltar que aunque los valores de consumo son los mínimos para esta familia de componentes, la potencia instantánea consumida sigue siendo muy alta para aquellos sistemas que han de trabajar distribuidos, de forma autónoma, y en la mayoría de los casos alimentados por baterías. Por esta razón, es necesario incluir en el diseño estrategias de ahorro energético para incrementar la usabilidad y el tiempo de vida de la plataforma. La primera estrategia implementada consiste en dividir la plataforma en distintas islas de alimentación de forma que sólo aquellos elementos que sean estrictamente necesarios permanecerán alimentados, cuando el resto puede estar completamente apagado. De esta forma es posible combinar distintos modos de operación y así optimizar enormemente el consumo de energía. El hecho de apagar la FPGA para ahora energía durante los periodos de inactividad, supone la pérdida de la configuración, puesto que la memoria de configuración es una memoria volátil. Para reducir el impacto en el consumo y en el tiempo que supone la reconfiguración total de la plataforma una vez encendida, en este trabajo, se incluye una técnica para la compresión del archivo de configuración de la FPGA, de forma que se consiga una reducción del tiempo de configuración y por ende de la energía consumida. Aunque varios de los requisitos de diseño pueden satisfacerse con el diseño de la plataforma HiReCookie, es necesario seguir optimizando diversos parámetros tales como el consumo energético, la tolerancia a fallos y la capacidad de procesamiento. Esto sólo es posible explotando todas las posibilidades ofrecidas por la arquitectura de procesamiento en la FPGA. Por lo tanto, la segunda parte de esta tesis doctoral está centrada en el diseño de una arquitectura reconfigurable denominada ARTICo3 (Arquitectura Reconfigurable para el Tratamiento Inteligente de Cómputo, Confiabilidad y Consumo de energía) para la mejora de estos parámetros por medio de un uso dinámico de recursos. ARTICo3 es una arquitectura de procesamiento para FPGAs basadas en RAM, con comunicación tipo bus, preparada para dar soporte para la gestión dinámica de los recursos internos de la FPGA en tiempo de ejecución gracias a la inclusión de reconfiguración dinámica y parcial. Gracias a esta capacidad de reconfiguración parcial, es posible adaptar los niveles de capacidad de procesamiento, energía consumida o tolerancia a fallos para responder a las demandas de la aplicación, entorno, o métricas internas del dispositivo mediante la adaptación del número de recursos asignados para cada tarea. Durante esta segunda parte de la tesis se detallan el diseño de la arquitectura, su implementación en la plataforma HiReCookie, así como en otra familia de FPGAs, y su validación por medio de diferentes pruebas y demostraciones. Los principales objetivos que se plantean la arquitectura son los siguientes: • Proponer una metodología basada en un enfoque multi-hilo, como las propuestas por CUDA (por sus siglas en inglés, Compute Unified Device Architecture) u Open CL, en la cual distintos kernels, o unidades de ejecución, se ejecuten en un numero variable de aceleradores hardware sin necesidad de cambios en el código de aplicación. • Proponer un diseño y proporcionar una arquitectura en la que las condiciones de trabajo cambien de forma dinámica dependiendo bien de parámetros externos o bien de parámetros que indiquen el estado de la plataforma. Estos cambios en el punto de trabajo de la arquitectura serán posibles gracias a la reconfiguración dinámica y parcial de aceleradores hardware en tiempo real. • Explotar las posibilidades de procesamiento concurrente, incluso en una arquitectura basada en bus, por medio de la optimización de las transacciones en ráfaga de datos hacia los aceleradores. •Aprovechar las ventajas ofrecidas por la aceleración lograda por módulos puramente hardware para conseguir una mejor eficiencia energética. • Ser capaces de cambiar los niveles de redundancia de hardware de forma dinámica según las necesidades del sistema en tiempo real y sin cambios para el código de aplicación. • Proponer una capa de abstracción entre el código de aplicación y el uso dinámico de los recursos de la FPGA. El diseño en FPGAs permite la utilización de módulos hardware específicamente creados para una aplicación concreta. De esta forma es posible obtener rendimientos mucho mayores que en el caso de las arquitecturas de propósito general. Además, algunas FPGAs permiten la reconfiguración dinámica y parcial de ciertas partes de su lógica en tiempo de ejecución, lo cual dota al diseño de una gran flexibilidad. Los fabricantes de FPGAs ofrecen arquitecturas predefinidas con la posibilidad de añadir bloques prediseñados y poder formar sistemas en chip de una forma más o menos directa. Sin embargo, la forma en la que estos módulos hardware están organizados dentro de la arquitectura interna ya sea estática o dinámicamente, o la forma en la que la información se intercambia entre ellos, influye enormemente en la capacidad de cómputo y eficiencia energética del sistema. De la misma forma, la capacidad de cargar módulos hardware bajo demanda, permite añadir bloques redundantes que permitan aumentar el nivel de tolerancia a fallos de los sistemas. Sin embargo, la complejidad ligada al diseño de bloques hardware dedicados no debe ser subestimada. Es necesario tener en cuenta que el diseño de un bloque hardware no es sólo su propio diseño, sino también el diseño de sus interfaces, y en algunos casos de los drivers software para su manejo. Además, al añadir más bloques, el espacio de diseño se hace más complejo, y su programación más difícil. Aunque la mayoría de los fabricantes ofrecen interfaces predefinidas, IPs (por sus siglas en inglés, Intelectual Property) comerciales y plantillas para ayudar al diseño de los sistemas, para ser capaces de explotar las posibilidades reales del sistema, es necesario construir arquitecturas sobre las ya establecidas para facilitar el uso del paralelismo, la redundancia, y proporcionar un entorno que soporte la gestión dinámica de los recursos. Para proporcionar este tipo de soporte, ARTICo3 trabaja con un espacio de soluciones formado por tres ejes fundamentales: computación, consumo energético y confiabilidad. De esta forma, cada punto de trabajo se obtiene como una solución de compromiso entre estos tres parámetros. Mediante el uso de la reconfiguración dinámica y parcial y una mejora en la transmisión de los datos entre la memoria principal y los aceleradores, es posible dedicar un número variable de recursos en el tiempo para cada tarea, lo que hace que los recursos internos de la FPGA sean virtualmente ilimitados. Este variación en el tiempo del número de recursos por tarea se puede usar bien para incrementar el nivel de paralelismo, y por ende de aceleración, o bien para aumentar la redundancia, y por lo tanto el nivel de tolerancia a fallos. Al mismo tiempo, usar un numero óptimo de recursos para una tarea mejora el consumo energético ya que bien es posible disminuir la potencia instantánea consumida, o bien el tiempo de procesamiento. Con el objetivo de mantener los niveles de complejidad dentro de unos límites lógicos, es importante que los cambios realizados en el hardware sean totalmente transparentes para el código de aplicación. A este respecto, se incluyen distintos niveles de transparencia: • Transparencia a la escalabilidad: los recursos usados por una misma tarea pueden ser modificados sin que el código de aplicación sufra ningún cambio. • Transparencia al rendimiento: el sistema aumentara su rendimiento cuando la carga de trabajo aumente, sin cambios en el código de aplicación. • Transparencia a la replicación: es posible usar múltiples instancias de un mismo módulo bien para añadir redundancia o bien para incrementar la capacidad de procesamiento. Todo ello sin que el código de aplicación cambie. • Transparencia a la posición: la posición física de los módulos hardware es arbitraria para su direccionamiento desde el código de aplicación. • Transparencia a los fallos: si existe un fallo en un módulo hardware, gracias a la redundancia, el código de aplicación tomará directamente el resultado correcto. • Transparencia a la concurrencia: el hecho de que una tarea sea realizada por más o menos bloques es transparente para el código que la invoca. Por lo tanto, esta tesis doctoral contribuye en dos líneas diferentes. En primer lugar, con el diseño de la plataforma HiReCookie y en segundo lugar con el diseño de la arquitectura ARTICo3. Las principales contribuciones de esta tesis se resumen a continuación. • Arquitectura de la HiReCookie incluyendo: o Compatibilidad con la plataforma Cookies para incrementar las capacidades de esta. o División de la arquitectura en distintas islas de alimentación. o Implementación de los diversos modos de bajo consumo y políticas de despertado del nodo. o Creación de un archivo de configuración de la FPGA comprimido para reducir el tiempo y el consumo de la configuración inicial. • Diseño de la arquitectura reconfigurable para FPGAs basadas en RAM ARTICo3: o Modelo de computación y modos de ejecución inspirados en el modelo de CUDA pero basados en hardware reconfigurable con un número variable de bloques de hilos por cada unidad de ejecución. o Estructura para optimizar las transacciones de datos en ráfaga proporcionando datos en cascada o en paralelo a los distinto módulos incluyendo un proceso de votado por mayoría y operaciones de reducción. o Capa de abstracción entre el procesador principal que incluye el código de aplicación y los recursos asignados para las diferentes tareas. o Arquitectura de los módulos hardware reconfigurables para mantener la escalabilidad añadiendo una la interfaz para las nuevas funcionalidades con un simple acceso a una memoria RAM interna. o Caracterización online de las tareas para proporcionar información a un módulo de gestión de recursos para mejorar la operación en términos de energía y procesamiento cuando además se opera entre distintos nieles de tolerancia a fallos. El documento está dividido en dos partes principales formando un total de cinco capítulos. En primer lugar, después de motivar la necesidad de nuevas plataformas para cubrir las nuevas aplicaciones, se detalla el diseño de la plataforma HiReCookie, sus partes, las posibilidades para bajar el consumo energético y se muestran casos de uso de la plataforma así como pruebas de validación del diseño. La segunda parte del documento describe la arquitectura reconfigurable, su implementación en varias FPGAs, y pruebas de validación en términos de capacidad de procesamiento y consumo energético, incluyendo cómo estos aspectos se ven afectados por el nivel de tolerancia a fallos elegido. Los capítulos a lo largo del documento son los siguientes: El capítulo 1 analiza los principales objetivos, motivación y aspectos teóricos necesarios para seguir el resto del documento. El capítulo 2 está centrado en el diseño de la plataforma HiReCookie y sus posibilidades para disminuir el consumo de energía. El capítulo 3 describe la arquitectura reconfigurable ARTICo3. El capítulo 4 se centra en las pruebas de validación de la arquitectura usando la plataforma HiReCookie para la mayoría de los tests. Un ejemplo de aplicación es mostrado para analizar el funcionamiento de la arquitectura. El capítulo 5 concluye esta tesis doctoral comentando las conclusiones obtenidas, las contribuciones originales del trabajo y resultados y líneas futuras. ABSTRACT This PhD Thesis is framed within the field of dynamically reconfigurable embedded systems, advanced sensor networks and distributed computing. The document is centred on the study of processing solutions for high-performance autonomous distributed systems (HPADS) as well as their evolution towards High performance Computing (HPC) systems. The approach of the study is focused on both platform and processor levels to optimise critical aspects such as computing performance, energy efficiency and fault tolerance. HPADS are considered feedback systems, normally networked and/or distributed, with real-time adaptive and predictive functionality. These systems, as part of more complex systems known as Cyber-Physical Systems (CPSs), can be applied in a wide range of fields such as military, health care, manufacturing, aerospace, etc. For the design of HPADS, high levels of dependability, the definition of suitable models of computation, and the use of methodologies and tools to support scalability and complexity management, are required. The first part of the document studies the different possibilities at platform design level in the state of the art, together with description, development and validation tests of the platform proposed in this work to cope with the previously mentioned requirements. The main objectives targeted by this platform design are the following: • Study the feasibility of using SRAM-based FPGAs as the main processor of the platform in terms of energy consumption and performance for high demanding applications. • Analyse and propose energy management techniques to reduce energy consumption in every stage of the working profile of the platform. • Provide a solution with dynamic partial and wireless remote HW reconfiguration (DPR) to be able to change certain parts of the FPGA design at run time and on demand without interrupting the rest of the system. • Demonstrate the applicability of the platform in different test-bench applications. In order to select the best approach for the platform design in terms of processing alternatives, a study of the evolution of the state-of-the-art platforms is required to analyse how different architectures cope with new more demanding applications and scenarios: security, mixed-critical systems for aerospace, multimedia applications, or military environments, among others. In all these scenarios, important changes in the required processing bandwidth or the complexity of the algorithms used are provoking the migration of the platforms from single microprocessor architectures to multiprocessing and heterogeneous solutions with more instant power consumption but higher energy efficiency. Within these solutions, FPGAs and Systems on Chip including FPGA fabric and dedicated hard processors, offer a good trade of among flexibility, processing performance, energy consumption and price, when they are used in demanding applications where working conditions are very likely to vary over time and high complex algorithms are required. The platform architecture proposed in this PhD Thesis is called HiReCookie. It includes an SRAM-based FPGA as the main and only processing unit. The FPGA selected, the Xilinx Spartan-6 LX150, was at the beginning of this work the best choice in terms of amount of resources and power. Although, the power levels are the lowest of these kind of devices, they can be still very high for distributed systems that normally work powered by batteries. For that reason, it is necessary to include different energy saving possibilities to increase the usability of the platform. In order to reduce energy consumption, the platform architecture is divided into different power islands so that only those parts of the systems that are strictly needed are powered on, while the rest of the islands can be completely switched off. This allows a combination of different low power modes to decrease energy. In addition, one of the most important handicaps of SRAM-based FPGAs is that they are not alive at power up. Therefore, recovering the system from a switch-off state requires to reload the FPGA configuration from a non-volatile memory device. For that reason, this PhD Thesis also proposes a methodology to compress the FPGA configuration file in order to reduce time and energy during the initial configuration process. Although some of the requirements for the design of HPADS are already covered by the design of the HiReCookie platform, it is necessary to continue improving energy efficiency, computing performance and fault tolerance. This is only possible by exploiting all the opportunities provided by the processing architectures configured inside the FPGA. Therefore, the second part of the thesis details the design of the so called ARTICo3 FPGA architecture to enhance the already intrinsic capabilities of the FPGA. ARTICo3 is a DPR-capable bus-based virtual architecture for multiple HW acceleration in SRAM-based FPGAs. The architecture provides support for dynamic resource management in real time. In this way, by using DPR, it will be possible to change the levels of computing performance, energy consumption and fault tolerance on demand by increasing or decreasing the amount of resources used by the different tasks. Apart from the detailed design of the architecture and its implementation in different FPGA devices, different validation tests and comparisons are also shown. The main objectives targeted by this FPGA architecture are listed as follows: • Provide a method based on a multithread approach such as those offered by CUDA (Compute Unified Device Architecture) or OpenCL kernel executions, where kernels are executed in a variable number of HW accelerators without requiring application code changes. • Provide an architecture to dynamically adapt working points according to either self-measured or external parameters in terms of energy consumption, fault tolerance and computing performance. Taking advantage of DPR capabilities, the architecture must provide support for a dynamic use of resources in real time. • Exploit concurrent processing capabilities in a standard bus-based system by optimizing data transactions to and from HW accelerators. • Measure the advantage of HW acceleration as a technique to boost performance to improve processing times and save energy by reducing active times for distributed embedded systems. • Dynamically change the levels of HW redundancy to adapt fault tolerance in real time. • Provide HW abstraction from SW application design. FPGAs give the possibility of designing specific HW blocks for every required task to optimise performance while some of them include the possibility of including DPR. Apart from the possibilities provided by manufacturers, the way these HW modules are organised, addressed and multiplexed in area and time can improve computing performance and energy consumption. At the same time, fault tolerance and security techniques can also be dynamically included using DPR. However, the inherent complexity of designing new HW modules for every application is not negligible. It does not only consist of the HW description, but also the design of drivers and interfaces with the rest of the system, while the design space is widened and more complex to define and program. Even though the tools provided by the majority of manufacturers already include predefined bus interfaces, commercial IPs, and templates to ease application prototyping, it is necessary to improve these capabilities. By adding new architectures on top of them, it is possible to take advantage of parallelization and HW redundancy while providing a framework to ease the use of dynamic resource management. ARTICo3 works within a solution space where working points change at run time in a 3D space defined by three different axes: Computation, Consumption, and Fault Tolerance. Therefore, every working point is found as a trade-off solution among these three axes. By means of DPR, different accelerators can be multiplexed so that the amount of available resources for any application is virtually unlimited. Taking advantage of DPR capabilities and a novel way of transmitting data to the reconfigurable HW accelerators, it is possible to dedicate a dynamically-changing number of resources for a given task in order to either boost computing speed or adding HW redundancy and a voting process to increase fault-tolerance levels. At the same time, using an optimised amount of resources for a given task reduces energy consumption by reducing instant power or computing time. In order to keep level complexity under certain limits, it is important that HW changes are transparent for the application code. Therefore, different levels of transparency are targeted by the system: • Scalability transparency: a task must be able to expand its resources without changing the system structure or application algorithms. • Performance transparency: the system must reconfigure itself as load changes. • Replication transparency: multiple instances of the same task are loaded to increase reliability and performance. • Location transparency: resources are accessed with no knowledge of their location by the application code. • Failure transparency: task must be completed despite a failure in some components. • Concurrency transparency: different tasks will work in a concurrent way transparent to the application code. Therefore, as it can be seen, the Thesis is contributing in two different ways. First with the design of the HiReCookie platform and, second with the design of the ARTICo3 architecture. The main contributions of this PhD Thesis are then listed below: • Architecture of the HiReCookie platform including: o Compatibility of the processing layer for high performance applications with the Cookies Wireless Sensor Network platform for fast prototyping and implementation. o A division of the architecture in power islands. o All the different low-power modes. o The creation of the partial-initial bitstream together with the wake-up policies of the node. • The design of the reconfigurable architecture for SRAM FPGAs: ARTICo3: o A model of computation and execution modes inspired in CUDA but based on reconfigurable HW with a dynamic number of thread blocks per kernel. o A structure to optimise burst data transactions providing coalesced or parallel data to HW accelerators, parallel voting process and reduction operation. o The abstraction provided to the host processor with respect to the operation of the kernels in terms of the number of replicas, modes of operation, location in the reconfigurable area and addressing. o The architecture of the modules representing the thread blocks to make the system scalable by adding functional units only adding an access to a BRAM port. o The online characterization of the kernels to provide information to a scheduler or resource manager in terms of energy consumption and processing time when changing among different fault-tolerance levels, as well as if a kernel is expected to work in the memory-bounded or computing-bounded areas. The document of the Thesis is divided into two main parts with a total of five chapters. First, after motivating the need for new platforms to cover new more demanding applications, the design of the HiReCookie platform, its parts and several partial tests are detailed. The design of the platform alone does not cover all the needs of these applications. Therefore, the second part describes the architecture inside the FPGA, called ARTICo3, proposed in this PhD Thesis. The architecture and its implementation are tested in terms of energy consumption and computing performance showing different possibilities to improve fault tolerance and how this impact in energy and time of processing. Chapter 1 shows the main goals of this PhD Thesis and the technology background required to follow the rest of the document. Chapter 2 shows all the details about the design of the FPGA-based platform HiReCookie. Chapter 3 describes the ARTICo3 architecture. Chapter 4 is focused on the validation tests of the ARTICo3 architecture. An application for proof of concept is explained where typical kernels related to image processing and encryption algorithms are used. Further experimental analyses are performed using these kernels. Chapter 5 concludes the document analysing conclusions, comments about the contributions of the work, and some possible future lines for the work.

Influence of castration on growth performance and carcass and meat quality of heavy female pigs

The main objetive of this Doctoral Thesis was to study the influence of female castration and pig sex on growth performance and carcass and meat quality of white pigs slaughtered at different final weights. Three experiments (Exp.) were conducted. In Exp. 1, a total of 200 (Landrace * Large White dam x Pietrain * Large White sire) gilts of 50 ± 3 days of age (23.3 ± 1.47 kg BW) was used to investigate the effects of castration (intact females, IF vs. castrated feamles, CF) and slaughter weight (106 vs. 122 kg BW) on productive performance and carcass and meat quality. There were four experimental treatments arranged as a 2 x 2 factorial and 5 replicates of 10 pigs each per treatment. Half of the gilts were ovariectomized at 58 d of age (8 days after the beginning of the trial; 29.8 ± 1.64 kg BW) whereas the other half remained intact. Meat samples were taken at m. Longissimus thoracis at the level of the last rib and subcutaneous fat samples were taken at the tail insertion. For the entire experiment period, CF had higher BW gain (P<0.05) and backfat and m. Gluteus medius (GM) fat thickness (P<0.001) than IF. However, IF had higher loin and trimmed primal cut yields (P<0.05) than CF. Meat quality was similar for IF and CF but the proportion of linoleic acid in subcutaneous fat was higher (P<0.001) for IF. Pigs slaughtered at 122 kg BW had higher (P<0.001) feed intake and poorer feed efficiency than pigs slaughtered at 106 kg BW. An increase in slaughter weight (SW) improved (P<0.001) carcass yield but decreased (P<0.05) trimmed primal cut yield. Meat from females slaughtered at the heavier BW was redder (a*; P<0.001) and had more (P<0.01) intramuscular fat and less thawing (P<0.05) and cooking (P<0.10) loss than meat from females slaughtered at the lighter BW. Also, females slaughtered at 122 kg BW had less (P<0.01) linoleic acid content in the subcutaneous fat than pigs slaughtered at 106 kg BW. Castration of gilts and slaughtering at heavier BW might be useful practices for the production of heavy pigs destined to the dry cured industry in which a certain amount of fat in the carcass is required. In contrast, when the carcasses are destined to fresh meat production, IF slaughtered at 106 kg BW are a more efficient alternative. In Exp. 2, crossbred pigs (n=240) from Pietrain*Large White sires mated to Landrace*Large White dams with an average of 100 d of age (60.5 ± 2.3 kg) were used to investigate the effects of gender and slaughter weight (SW) on growth performance and carcass and meat quality characteristics. There were 6 treatments arranged factorially with 3 genders (IF vs. CF vs.castrated males, CM) and 2 SW (114 vs. 122 kg BW). Each of the 6 combinations of treatments was replicated 4 times and the experimental unit was a pen with 10 pigs. Castrated males and CF ate more feed, grew faster and had more carcass backfat depth and fat thickness at the GM muscle, but lower loin yield than IF (P<0.05). In addition, CF and CM had more intramuscular fat (P<0.05) and less linoleic acid content in the subcutaneous fat (P<0.01) than IF. Pigs slaughtered at 122 kg BW had lower ADG (P<0.05), poor gain-to-feed ratio (P<0.05), and more GM fat than pigs slaughtered at 114 kg BW (P < 0.05). It is concluded that CF and CM had similar productive performance and meat quality characteristics when slaughtered at the same age, and that the castration of females improved daily gains and increased weight and fat content of primal cuts with respect to IF. Therefore, castration of females is recommended in pigs destined to the dry-cured industry because of the beneficial effects on the quality of the primal cuts. In Exp. 3, the effects of gender and castration of females (IF vs. CF vs. CM) on performance and carcass and meat quality were studied in crossbred pigs (Landrace x Large White dams x Duroc sires) slaughtered at 119.2 (trial 1) or 131.6 (trial 2) kg BW. Intact females had better feed conversion and less carcass fat than CF and CM. Trimmed shoulder yield was higher for CM than for CF with IF being intermediate. Primal cut yield and meat quality, however were similar for all treatments. Proportion of linoleic acid in backfat was lower for CF than for IF or CM, and the differences were significant in pigs slaughtered witn 131.6 kg BW. The higher fat content and the fatty acid profile favour the use of CF and CM over IF for the production of heavy pigs destined to the dry-cured industry.

Effect of Sb on the quantum efficiency of GaInP solar cells

The energy bandgap of GaInP solar cells can be tuned by modifying the degree of order of the alloy. In this study, we employed Sb to increase the energy bandgap of the GaInP and analyzed its impact on the performance of GaInP solar cells. An effective change in the cutoff wavelength of the external quantum efficiency of GaInP solar cells and an effective increase of 50 mV in the open-circuit voltage of GaInP/Ga(In)As/Ge triple junction solar cells were obtained with the use of Sb. Copyright © 2016 John Wiley & Sons, Ltd.