927 resultados para minimalist hardware architecture


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This paper presents a Radix-4(3) based FFT architecture suitable for OFDM based WLAN applications. The radix-4(3) parallel unrolled architecture presented here, uses a radix-4 butterfly unit which takes all four inputs in parallel and can selectively produce one out of the four outputs. A 64 point FFT processor based on the proposed architecture has been implemented in UMC 130nm 1P8M CMOS process with a maximum clock frequency of 100 MHz and area of 0.83mm(2). The proposed processor provides a throughput of four times the clock rate and can finish one 64 point FFT computation in 16 clock cycles. For IEEE 802.11a/g WLAN, the processor needs to be operated at a clock rate of 5 MHz with a power consumption of 2.27 mW which is 27% less than the previously reported low power implementations.

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In this paper we present a framework for realizing arbitrary instruction set extensions (IE) that are identified post-silicon. The proposed framework has two components viz., an IE synthesis methodology and the architecture of a reconfigurable data-path for realization of the such IEs. The IE synthesis methodology ensures maximal utilization of resources on the reconfigurable data-path. In this context we present the techniques used to realize IEs for applications that demand high throughput or those that must process data streams. The reconfigurable hardware called HyperCell comprises a reconfigurable execution fabric. The fabric is a collection of interconnected compute units. A typical use case of HyperCell is where it acts as a co-processor with a host and accelerates execution of IEs that are defined post-silicon. We demonstrate the effectiveness of our approach by evaluating the performance of some well-known integer kernels that are realized as IEs on HyperCell. Our methodology for realizing IEs through HyperCells permits overlapping of potentially all memory transactions with computations. We show significant improvement in performance for streaming applications over general purpose processor based solutions, by fully pipelining the data-path. (C) 2014 Elsevier B.V. All rights reserved.

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The current manuscript describes conformational analysis of 15-membered cyclic tetrapeptides (CTPs), with alpha 3 delta architecture, containing sugar amino acids (SAA) having variation in the stereocenter at C5 carbon. Conformational analyses of both the series, in protected and deprotected forms, were carried out in DMSO-d(6) using various NMR techniques, supported by restrained MD calculations. It was intriguing to notice that the alpha 3 delta macrocycles got stabilized by both 10-membered beta-turn as well as a seven-membered gamma-turn, fused within the same macrocycle. The presence of fused sub-structures within a 15-membered macrocycle is rare to see. Also, the stereocenter variation at C5 did not affect the fused turn structures and exhibited similar conformations in both the series. The design becomes highly advantageous as fused reverse turn structures are occurring in the cyclic structure with minimalistic size macrocycle and this can be applied to develop suitable pharmacophores in the drug development process. (C) 2014 Elsevier Ltd. All rights reserved.

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A Field Programmable Gate Array (FPGA) based hardware accelerator for multi-conductor parasitic capacitance extraction, using Method of Moments (MoM), is presented in this paper. Due to the prohibitive cost of solving a dense algebraic system formed by MoM, linear complexity fast solver algorithms have been developed in the past to expedite the matrix-vector product computation in a Krylov sub-space based iterative solver framework. However, as the number of conductors in a system increases leading to a corresponding increase in the number of right-hand-side (RHS) vectors, the computational cost for multiple matrix-vector products present a time bottleneck, especially for ill-conditioned system matrices. In this work, an FPGA based hardware implementation is proposed to parallelize the iterative matrix solution for multiple RHS vectors in a low-rank compression based fast solver scheme. The method is applied to accelerate electrostatic parasitic capacitance extraction of multiple conductors in a Ball Grid Array (BGA) package. Speed-ups up to 13x over equivalent software implementation on an Intel Core i5 processor for dense matrix-vector products and 12x for QR compressed matrix-vector products is achieved using a Virtex-6 XC6VLX240T FPGA on Xilinx's ML605 board.

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The steady-state negative supercoiling of eubacterial genomes is maintained by the action of DNA topoisomerases. Topoisomerase distribution varies in different species of mycobacteria. While Mycobacterium tuberculosis (Mtb) contains a single type I (Topol) and a single type II (Gyrase) enzyme, Mycobacterium smegmatis (Msm) and other members harbour additional relaxases. Topol is essential for Mtb survival. However, the necessity of Topol or other relaxases in Msm has not been investigated. To recognize the importance of Topol for growth, physiology and gene expression of Msm, we have developed a conditional knock-down strain of Topol in Msm. The Topol-depleted strain exhibited extremely slow growth and drastic changes in phenotypic characteristics. The cessation of growth indicates the essential requirement of the enzyme for the organism in spite of having additional DNA relaxation enzymes in the cell. Notably, the imbalance in Topol level led to the altered expression of topology modulatory proteins, resulting in a diffused nucleoid architecture. Proteomic and transcript analysis of the mutant indicated reduced expression of the genes involved in central metabolic pathways and core DNA transaction processes. RNA polymerase (RNAP) distribution on the transcription units was affected in the Topol-depleted cells, suggesting global alteration in transcription. The study thus highlights the essential requirement of Topol in the maintenance of cellular phenotype, growth characteristics and gene expression in mycobacteria. A decrease in Topol level led to altered RNAP occupancy and impaired transcription elongation, causing severe downstream effects.

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We propose an architecture for dramatically enhancing the stress bearing and energy absorption capacities of a polymer based composite. Different weight fractions of iron oxide nano-particles (NPs) are mixed in a poly(dimethylesiloxane) (PDMS) matrix either uniformly or into several vertically aligned cylindrical pillars. These composites are compressed up to a strain of 60% at a strain rate of 0.01 s(-1) following which they are fully unloaded at the same rate. Load bearing and energy absorption capacities of the composite with uniform distribution of NPs increase by similar to 50% upon addition of 5 wt% of NPs; however, these properties monotonically decrease with further addition of NPs so much so that the load bearing capacity of the composite becomes 1/6th of PDMS upon addition of 20 wt% of NPs. On the contrary, stress at a strain of 60% and energy absorption capacity of the composites with pillar configuration monotonically increase with the weight fraction of NPs in the pillars wherein the load bearing capacity becomes 1.5 times of PDMS when the pillars consisted of 20 wt% of NPs. In situ mechanical testing of composites with pillars reveals outward bending of the pillars wherein the pillars and the PDMS in between two pillars, located along a radius, are significantly compressed. Reasoning based on effects of compressive hydrostatic stress and shape of fillers is developed to explain the observed anomalous strengthening of the composite with pillar architecture.

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An abundance of spectrum access and sensing algorithms are available in the dynamic spectrum access (DSA) and cognitive radio (CR) literature. Often, however, the functionality and performance of such algorithms are validated against theoretical calculations using only simulations. Both the theoretical calculations and simulations come with their attendant sets of assumptions. For instance, designers of dynamic spectrum access algorithms often take spectrum sensing and rendezvous mechanisms between transmitter-receiver pairs for granted. Test bed designers, on the other hand, either customize so much of their design that it becomes difficult to replicate using commercial off the shelf (COTS) components or restrict themselves to simulation, emulation /hardware-in-Ioop (HIL), or pure hardware but not all three. Implementation studies on test beds sophisticated enough to combine the three aforementioned aspects, but at the same time can also be put together using COTS hardware and software packages are rare. In this paper we describe i) the implementation of a hybrid test bed using a previously proposed hardware agnostic system architecture ii) the implementation of DSA on this test bed, and iii) the realistic hardware and software-constrained performance of DSA. Snapshot energy detector (ED) and Cumulative Summation (CUSUM), a sequential change detection algorithm, are available for spectrum sensing and a two-way handshake mechanism in a dedicated control channel facilitates transmitter-receiver rendezvous.

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Graph algorithms have been shown to possess enough parallelism to keep several computing resources busy-even hundreds of cores on a GPU. Unfortunately, tuning their implementation for efficient execution on a particular hardware configuration of heterogeneous systems consisting of multicore CPUs and GPUs is challenging, time consuming, and error prone. To address these issues, we propose a domain-specific language (DSL), Falcon, for implementing graph algorithms that (i) abstracts the hardware, (ii) provides constructs to write explicitly parallel programs at a higher level, and (iii) can work with general algorithms that may change the graph structure (morph algorithms). We illustrate the usage of our DSL to implement local computation algorithms (that do not change the graph structure) and morph algorithms such as Delaunay mesh refinement, survey propagation, and dynamic SSSP on GPU and multicore CPUs. Using a set of benchmark graphs, we illustrate that the generated code performs close to the state-of-the-art hand-tuned implementations.

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Scaffolds for bone tissue engineering are essentially characterized by porous three-dimensional structures with interconnected pores to facilitate the exchange of nutrients and removal of waste products from cells, thereby promoting cell proliferation in such engineered scaffolds. Although hydroxyapatite is widely being considered for bone tissue engineering applications due to its occurrence in the natural extracellular matrix of this tissue, limited reports are available on additive manufacturing of hydroxyapatite-based materials. In this perspective, hydroxyapatite-based three-dimensional porous scaffolds with two different binders (maltodextrin and sodium alginate) were fabricated using the extrusion method of three-dimensional plotting and the results were compared in reference to the structural properties of scaffolds processed via chemical stabilization and sintering routes, respectively. With the optimal processing conditions regarding to pH and viscosity of binder-loaded hydroxyapatite pastes, scaffolds with parallelepiped porous architecture having up to 74% porosity were fabricated. Interestingly, sintering of the as-plotted hydroxyapatite-sodium alginate (cross-linked with CaCl2 solution) scaffolds led to the formation of chlorapatite (Ca9.54P5.98O23.8Cl1.60(OH)(2.74)). Both the sintered scaffolds displayed progressive deformation and delayed fracture under compressive loading, with hydroxyapatite-alginate scaffolds exhibiting a higher compressive strength (9.5 +/- 0.5MPa) than hydroxyapatite-maltodextrin scaffolds (7.0 +/- 0.6MPa). The difference in properties is explained in terms of the phase assemblage and microstructure.

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We discuss the potential application of high dc voltage sensing using thin-film transistors (TFTs) on flexible substrates. High voltage sensing has potential applications for power transmission instrumentation. For this, we consider a gate metal-substrate-semiconductor architecture for TFTs. In this architecture, the flexible substrate not only provides mechanical support but also plays the role of the gate dielectric of the TFT. Hence, the thickness of the substrate needs to be optimized for maximizing transconductance, minimizing mechanical stress, and minimizing gate leakage currents. We discuss this optimization, and develop n-type and p-type organic TFTs using polyvinyldene fluoride as the substrate-gate insulator. Circuits are also realized to achieve level shifting, amplification, and high drain voltage operation.

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Human Guanine Monophosphate Synthetase (hGMPS) converts XMP to GMP, and acts as a bifunctional enzyme with N-terminal ``glutaminase'' (GAT) and C-terminal ``synthetase'' domain. The enzyme is identified as a potential target for anticancer and immunosuppressive therapies. GAT domain of enzyme plays central role in metabolism, and contains conserved catalytic residues Cys104, His190, and Glu192. MD simulation studies on GAT domain suggest that position of oxyanion in unliganded conformation is occupied by one conserved water molecule (W1), which also stabilizes that pocket. This position is occupied by a negatively charged atom of the substrate or ligand in ligand bound crystal structures. In fact, MD simulation study of Ser75 to Val indicates that W1 conserved water molecule is stabilized by Ser75, while Thr152, and His190 also act as anchor residues to maintain appropriate architecture of oxyanion pocket through water mediated H-bond interactions. Possibly, four conserved water molecules stabilize oxyanion hole in unliganded state, but they vacate these positions when the enzyme (hGMPS)-substrate complex is formed. Thus this study not only reveals functionally important role of conserved water molecules in GAT domain, but also highlights essential role of other non-catalytic residues such as Ser75 and Thr152 in this enzymatic domain. The results from this computational study could be of interest to experimental community and provide a testable hypothesis for experimental validation. Conserved sites of water molecules near and at oxyanion hole highlight structural importance of water molecules and suggest a rethink of the conventional definition of chemical geometry of inhibitor binding site.

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The effects of contact architecture, graphene defect density and metal-semiconductor work function difference on the resistivity of metal-graphene contacts have been investigated. An architecture with metal on the bottom of graphene is found to yield resistivities that are lower, by a factor of four, and most consistent as compared to metal on top of graphene. Growth defects in graphene film were found to further reduce resistivity by a factor of two. Using a combination of method and metal used, the contact resistivity of graphene has been decreased by a factor of 10 to 1200. +/-. 250 Omega mu m using palladium as the contact metal. While the improved consistency is due to the metal being able to contact uncontaminated graphene in the metal on the bottom architecture, lower contact resistivities observed on defective graphene with the same metal are attributed to the increased number of modes of quantum transport in the channel.

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The aim of this paper is to describe the implementation of a new approach for the introduction of so called 'holonic manufacturing' principles into existing production control systems. Such an approach is intended to improve the reconfigurability of the control system to cope with the increasing requirements of production change. A conceptual architecture is described and implemented in a robot assembly cell to demonstrate that this approach can lead to a manufacturing control system which can adapt relatively simply to long-term change. A design methodology and migration strategy for achieving these solutions using conventional hardware is proposed to develop execution level of manufacturing control systems.

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This short communication presents our recent studies to implement numerical simulations for multi-phase flows on top-ranked supercomputer systems with distributed memory architecture. The numerical model is designed so as to make full use of the capacity of the hardware. Satisfactory scalability in terms of both the parallel speed-up rate and the size of the problem has been obtained on two high rank systems with massively parallel processors, the Earth Simulator (Earth simulator research center, Yokohama Kanagawa, Japan) and the TSUBAME (Tokyo Institute of Technology, Tokyo, Japan) supercomputers.