Uma arquitetura distribuída de hardware e software para controle de um robô móvel autônomo

In this work, we present a hardware-software architecture for controlling the autonomous mobile robot Kapeck. The hardware of the robot is composed of a set of sensors and actuators organized in a CAN bus. Two embedded computers and eigth microcontroller based boards are used in the system. One of the computers hosts the vision system, due to the significant processing needs of this kind of system. The other computer is used to coordinate and access the CAN bus and to accomplish the other activities of the robot. The microcontroller-based boards are used with the sensors and actuators. The robot has this distributed configuration in order to exhibit a good real-time behavior, where the response time and the temporal predictability of the system is important. We adopted the hybrid deliberative-reactive paradigm in the proposed architecture to conciliate the reactive behavior of the sensors-actuators net and the deliberative activities required to accomplish more complex tasks

Metodologia para adaptação de microarquiteturas microprogramadas soft-core à uma ISA padrão: estudo do impacto sobre a complexidade de hardware para o padrão MIPS

In academia, it is common to create didactic processors, facing practical disciplines in the area of Hardware Computer and can be used as subjects in software platforms, operating systems and compilers. Often, these processors are described without ISA standard, which requires the creation of compilers and other basic software to provide the hardware / software interface and hinder their integration with other processors and devices. Using reconfigurable devices described in a HDL language allows the creation or modification of any microarchitecture component, leading to alteration of the functional units of data path processor as well as the state machine that implements the control unit even as new needs arise. In particular, processors RISP enable modification of machine instructions, allowing entering or modifying instructions, and may even adapt to a new architecture. This work, as the object of study addressing educational soft-core processors described in VHDL, from a proposed methodology and its application on two processors with different complexity levels, shows that it s possible to tailor processors for a standard ISA without causing an increase in the level hardware complexity, ie without significant increase in chip area, while its level of performance in the application execution remains unchanged or is enhanced. The implementations also allow us to say that besides being possible to replace the architecture of a processor without changing its organization, RISP processor can switch between different instruction sets, which can be expanded to toggle between different ISAs, allowing a single processor become adaptive hybrid architecture, which can be used in embedded systems and heterogeneous multiprocessor environments

Uma implementação da análise de componentes independentes em plataforma de hardware reconfigurável

Blind Source Separation (BSS) refers to the problem of estimate original signals from observed linear mixtures with no knowledge about the sources or the mixing process. Independent Component Analysis (ICA) is a technique mainly applied to BSS problem and from the algorithms that implement this technique, FastICA is a high performance iterative algorithm of low computacional cost that uses nongaussianity measures based on high order statistics to estimate the original sources. The great number of applications where ICA has been found useful reects the need of the implementation of this technique in hardware and the natural paralelism of FastICA favors the implementation of this algorithm on digital hardware. This work proposes the implementation of FastICA on a reconfigurable hardware platform for the viability of it's use in blind source separation problems, more specifically in a hardware prototype embedded in a Field Programmable Gate Array (FPGA) board for the monitoring of beds in hospital environments. The implementations will be carried out by Simulink models and it's synthesizing will be done through the DSP Builder software from Altera Corporation.

Desenvolvimento de uma arquitetura em hardware prototipada em FPGA para aplicações genéricas utilizando redes neurais artificiais embarcadas

This work proposes hardware architecture, VHDL described, developed to embedded Artificial Neural Network (ANN), Multilayer Perceptron (MLP). The present work idealizes that, in this architecture, ANN applications could easily embed several different topologies of MLP network industrial field. The MLP topology in which the architecture can be configured is defined by a simple and specifically data input (instructions) that determines the layers and Perceptron quantity of the network. In order to set several MLP topologies, many components (datapath) and a controller were developed to execute these instructions. Thus, an user defines a group of previously known instructions which determine ANN characteristics. The system will guarantee the MLP execution through the neural processors (Perceptrons), the components of datapath and the controller that were developed. In other way, the biases and the weights must be static, the ANN that will be embedded must had been trained previously, in off-line way. The knowledge of system internal characteristics and the VHDL language by the user are not needed. The reconfigurable FPGA device was used to implement, simulate and test all the system, allowing application in several real daily problems

Implementação de processador banda base ofdma para downlink lte em fpga

This work treats of an implementation OFDMA baseband processor in hardware for LTE Downlink. The LTE or Long Term Evolution consist the last stage of development of the technology called 3G (Mobile System Third Generation) which offers an increasing in data rate and more efficiency and flexibility in transmission with application of advanced antennas and multiple carriers techniques. This technology applies in your physical layer the OFDMA technical (Orthogonal Frequency Division Multiple Access) for generation of signals and mapping of physical resources in downlink and has as base theoretical to OFDM multiple carriers technique (Orthogonal Frequency Division Multiplexing). With recent completion of LTE specifications, different hardware solutions have been developed, mainly, to the level symbol processing where the implementation of OFDMA processor in base band is commonly considered, because it is also considered a basic architecture of others important applications. For implementation of processor, the reconfigurable hardware offered by devices as FPGA are considered which shares not only to meet the high requirements of flexibility and adaptability of LTE as well as offers possibility of an implementation quick and efficient. The implementation of processor in reconfigurable hardware meets the specifications of LTE physical layer as well as have the flexibility necessary for to meet others standards and application which use OFDMA processor as basic architecture for your systems. The results obtained through of simulation and verification functional system approval the functionality and flexibility of processor implemented

Acelerando algoritmos de baixo nível em visão robótica com hardware reconfigurável

A challenge that remains in the robotics field is how to make a robot to react in real time to visual stimulus. Traditional computer vision algorithms used to overcome this problem are still very expensive taking too long when using common computer processors. Very simple algorithms like image filtering or even mathematical morphology operations may take too long. Researchers have implemented image processing algorithms in high parallelism hardware devices in order to cut down the time spent in the algorithms processing, with good results. By using hardware implemented image processing techniques and a platform oriented system that uses the Nios II Processor we propose an approach that uses the hardware processing and event based programming to simplify the vision based systems while at the same time accelerating some parts of the used algorithms

Immobilization of uricase in layer-by-layer films used in amperometric biosensors for uric acid

The layer-by-layer technique was exploited to immobilize the enzyme uricase onto indium tin oxide substrates coated with a layer of Prussian Blue. Uricase layers were alternated with either poly(ethylene imine) or poly(diallyidimethylammoniumchloride), and the resulting films were used as amperometric biosensors for uric acid. Biosensors with optimum perfomance had a limit of detection of 0.15 mu A mu mol 1(-1) cm(-2) with a linear response between 0.1 and 0.6 mu M of uric acid, which is sufficient for use in clinical tests. Bioactivity was preserved for weeks, and there was negligible influence from interferents, as detection was carried out at 0.0 V vs saturated calomel electrode.

A layer-by-layer film of chitosan in a taste sensor application

Chitosan is alternated with sulfonated polystyrene (PSS) to build layer-by-layer (LBL) films that are used as sensing units in an electronic tongue. Using impedance spectroscopy as the principle method of detection, an array using chitosan/PSS LBL film and a bare gold electrode as the sensing units was capable of distinguishing the basic tastes - salty, sweet, bitter, and sour - to a concentration below the human threshold. The suitability of chitosan as a sensing material was confirmed by using this sensor to distinguish red wines according to their vintage, vineyard, and brands.

Effect of ion concentration of ionomer in electron injection layer of polymer light-emitting devices

Polymer light-emitting devices (PLEDs) with poly(2-methoxy-5-hexyloxy)-p-phenylenevinylene (OC1OC6-PPV) as the emissive layer were studied with an electron injection layer of ionomers consisting of copolymers of styrene and methylmethacrylate (PS/PMMA) with 3, 6 and 8 mol% degree of sulfonation. The ionomers were able to form very thin films over the emissive layer, with less than 30 nm. Additionally, the presence of ion pairs of ionomer suppresses the tendency toward dewetting of the thin film of ionomer (similar to 10 nm) which can cause malfunction of the device. The effect of the ionomers was investigated as a function of the ion content. The devices performance, characterized by their current density and luminance intensity versus voltage, showed a remarkable increase with the ionomer layer up to 6 mol% of ionic groups, decreasing after that for the 8 mol% ionomer device. The study of the impedance spectroscopy in the frequency range from 0.1 to 10(6) Hz showed that the injection phenomena dominate over the transport in the electroluminescent polymer bulk. (c) 2006 Elsevier B.V. All rights reserved.

Polymer light emitting devices with Langmuir-Blodgett (LB) films: Enhanced performance due to an electron-injecting layer of ionomers

Polymer light-emitting devices (PLEDs) have been produced with Langmuir-Blodgett (LB) films from poly(2-methoxy-5-hexyloxy)-p-phenylenevinylene (OC1OC6-PPV) as the emissive layer and an ionomer of a copolymer of styrene and methylmethacrylate (PS/PMMA) as an electron-injection layer. The main features of such devices are the low operating voltages, obtainable firstly due to the good quality of the ultrathin LB films that allows PLEDs to be produced reproducibly and secondly due to the improved electrical and luminance properties brought by the electron-injection layer. Also demonstrated is the superior performance of an all-LB device compared to another one produced with cast films of the same materials. Published by Elsevier B.V.

Layer by layer TiO2 thin films and photodegradation of Congo red

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

Incorporation of Ag nanoparticles into membrane mimetic systems composed by phospholipid layer-by-layer (LbL) films to achieve surface-enhanced Raman scattering as a tool in drug interaction studies

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

Monomolecular films of cholesterol oxidase and S-Layer proteins

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

Iron phthalocyanine in non-aqueous medium forming layer-by-layer films: growth mechanism, molecular architecture and applications

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

Layer-by-Layer Technique as a New Approach to Produce Nanostructured Films Containing Phospholipids as Transducers in Sensing Applications

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)