A zero charge-pump mismatch current tracking loop for reference spur reduction in PLLs

The charge-pump (CP) mismatch current is a dominant source of static phase error and reference spur in the nano-meter CMOS PLL implementations due to its worsened channel length modulation effect. This paper presents a charge-pump (CP) mismatch current reduction technique utilizing an adaptive body bias tuning of CP transistors and a zero CP mismatch current tracking PLL architecture for reference spur suppression. A chip prototype of the proposed circuit was implemented in 0.13 mu m CMOS technology. The frequency synthesizer consumes 8.2 mA current from a 13 V supply voltage and achieves a phase noise of -96.01 dBc/Hz @ 1 MHz offset from a 2.4 GHz RF carrier. The charge-pump measurements using the proposed calibration technique exhibited a mismatch current of less than 0.3 mu A (0.55%) over the VCO control voltage range of 0.3-1.0 V. The closed loop measurements show a minimized static phase error of within +/- 70 ps and a similar or equal to 9 dB reduction in reference spur level across the PLL output frequency range 2.4-2.5 GHz. The presented CP calibration technique compensates for the DC current mismatch and the mismatch due to channel length modulation effect and therefore improves the performance of CP-PLLs in nano-meter CMOS implementations. (C) 2015 Elsevier Ltd. All rights reserved.

Suspended core-shell Pt-PtOx nanostructure for ultrasensitive hydrogen gas sensor

High sensitivity gas sensors are typically realized using metal catalysts and nanostructured materials, utilizing non-conventional synthesis and processing techniques, incompatible with on-chip integration of sensor arrays. In this work, we report a new device architecture, suspended core-shell Pt-PtOx nanostructure that is fully CMOS-compatible. The device consists of a metal gate core, embedded within a partially suspended semiconductor shell with source and drain contacts in the anchored region. The reduced work function in suspended region, coupled with builtin electric field of metal-semiconductor junction, enables the modulation of drain current, due to room temperature Redox reactions on exposure to gas. The device architecture is validated using Pt-PtO2 suspended nanostructure for sensing H-2 down to 200 ppb under room temperature. By exploiting catalytic activity of PtO2, in conjunction with its p-type semiconducting behavior, we demonstrate about two orders of magnitude improvement in sensitivity and limit of detection, compared to the sensors reported in recent literature. Pt thin film, deposited on SiO2, is lithographically patterned and converted into suspended Pt-PtO2 sensor, in a single step isotropic SiO2 etching. An optimum design space for the sensor is elucidated with the initial Pt film thickness ranging between 10 nm and 30 nm, for low power (< 5 mu W), room temperature operation. (C) 2015 AIP Publishing LLC.

Router Attack toward NoC-enabled MPSoC and Monitoring Countermeasures against such Threat

The growing number of applications and processing units in modern Multiprocessor Systems-on-Chips (MPSoCs) come along with reduced time to market. Different IP cores can come from different vendors, and their trust levels are also different, but typically they use Network-on-Chip (NoC) as their communication infrastructure. An MPSoC can have multiple Trusted Execution Environments (TEEs). Apart from performance, power, and area research in the field of MPSoC, robust and secure system design is also gaining importance in the research community. To build a secure system, the designer must know beforehand all kinds of attack possibilities for the respective system (MPSoC). In this paper we survey the possible attack scenarios on present-day MPSoCs and investigate a new attack scenario, i.e., router attack targeted toward NoC architecture. We show the validity of this attack by analyzing different present-day NoC architectures and show that they are all vulnerable to this type of attack. By launching a router attack, an attacker can control the whole chip very easily, which makes it a very serious issue. Both routing tables and routing logic-based routers are vulnerable to such attacks. In this paper, we address attacks on routing tables. We propose different monitoring-based countermeasures against routing table-based router attack in an MPSoC having multiple TEEs. Synthesis results show that proposed countermeasures, viz. Runtime-monitor, Restart-monitor, Intermediate manager, and Auditor, occupy areas that are 26.6, 22, 0.2, and 12.2 % of a routing table-based router area. Apart from these, we propose Ejection address checker and Local monitoring module inside a router that cause 3.4 and 10.6 % increase of a router area, respectively. Simulation results are also given, which shows effectiveness of proposed monitoring-based countermeasures.

Co-Exploration of NLA Kernels and Specification of Compute Elements in Distributed Memory CGRAs

Coarse Grained Reconfigurable Architectures (CGRA) are emerging as embedded application processing units in computing platforms for Exascale computing. Such CGRAs are distributed memory multi- core compute elements on a chip that communicate over a Network-on-chip (NoC). Numerical Linear Algebra (NLA) kernels are key to several high performance computing applications. In this paper we propose a systematic methodology to obtain the specification of Compute Elements (CE) for such CGRAs. We analyze block Matrix Multiplication and block LU Decomposition algorithms in the context of a CGRA, and obtain theoretical bounds on communication requirements, and memory sizes for a CE. Support for high performance custom computations common to NLA kernels are met through custom function units (CFUs) in the CEs. We present results to justify the merits of such CFUs.

Fin-Enabled-Area-Scaled Tunnel FET

While keeping the technological evolution and commercialization of FinFET technology in mind, this paper discloses a novel concept that enables area-scaled or vertical tunneling in Fin-based technologies. The concept provides a roadmap for beyond FinFET technologies, while enjoying the advantages of FinFET-like structure without demanding technological abruptness from the existing FinFET technology nodes to beyond FinFET nodes. The proposed device at 10-nm gate length, when compared with the conventional vertical tunneling FET or planar area-scaled device, offers 100% improvement in the ON-current, 15x reduction in the OFF-current, 3x increase in the transconductance, 30% improvement in the output resistance, 55% improvement in the unity gain frequency, and more importantly 6x reduction in the footprint area for a given drive capability. Furthermore, the proposed device brings the average and minimum subthreshold slope down to 40 and 11 mV/decade at 10-nm gate length. This gives a path for beyond FinFET system-on-chip applications, while enjoying the analog, digital, and RF performance improvements.

Part II: Design of Well Doping Profile for Improved Breakdown and Mixed-Signal Performance of STI-Type DePMOS Device

Shallow-trench isolation drain extended pMOS (STI-DePMOS) devices show a distinct two-stage breakdown. The impact of p-well and deep-n-well doping profile on breakdown characteristics is investigated based on TCAD simulations. Design guidelines for p-well and deep-n-well doping profile are developed to shift the onset of the first-stage breakdown to a higher drain voltage and to avoid vertical punch-through leading to early breakdown. An optimal ratio between the OFF-state breakdown voltage and the ON-state resistance could be obtained. Furthermore, the impact of p-well/deep-n-well doping profile on the figure of merits of analog and digital performance is studied. This paper aids in the design of STI drain extended MOSFET devices for widest safe operating area and optimal mixed-signal performance in advanced system-on-chip input-output process technologies.

A Mitigation Technique for Harmonic Downconversion in Wideband Spectrum Sensors

The down conversion of radio frequency components around the harmonics of the local oscillator (LO), and its impact on the accuracy of white space detection using integrated spectrum sensors, is studied. We propose an algorithm to mitigate the impact of harmonic downconversion by utilizing multiple parallel downconverters in the system architecture. The proposed algorithm is validated on a test-board using commercially available integrated circuits and a test-chip implemented in a 130-nm CMOS technology. The measured data show that the impact of the harmonic downconversion is closely related to the LO characteristics, and that much of it can be mitigated by the proposed technique.

Bi-Modal DRAM Cache: Improving Hit Rate, Hit Latency and Bandwidth

In this paper, we present Bi-Modal Cache - a flexible stacked DRAM cache organization which simultaneously achieves several objectives: (i) improved cache hit ratio, (ii) moving the tag storage overhead to DRAM, (iii) lower cache hit latency than tags-in-SRAM, and (iv) reduction in off-chip bandwidth wastage. The Bi-Modal Cache addresses the miss rate versus off-chip bandwidth dilemma by organizing the data in a bi-modal fashion - blocks with high spatial locality are organized as large blocks and those with little spatial locality as small blocks. By adaptively selecting the right granularity of storage for individual blocks at run-time, the proposed DRAM cache organization is able to make judicious use of the available DRAM cache capacity as well as reduce the off-chip memory bandwidth consumption. The Bi-Modal Cache improves cache hit latency despite moving the metadata to DRAM by means of a small SRAM based Way Locator. Further by leveraging the tremendous internal bandwidth and capacity that stacked DRAM organizations provide, the Bi-Modal Cache enables efficient concurrent accesses to tags and data to reduce hit time. Through detailed simulations, we demonstrate that the Bi-Modal Cache achieves overall performance improvement (in terms of Average Normalized Turnaround Time (ANTT)) of 10.8%, 13.8% and 14.0% in 4-core, 8-core and 16-core workloads respectively.

Enhancement Mechanism of Fluorescence Intensity in Presence of Plasmonic Nanoparticles

The emission intensity of fluorophore molecule may change in presence of strong plasmon field induced by nanoparticles. The enhancement intensity is optimized through selective clustering or functionalization of nanoparticles in closed vicinity of fluorophore. Our study is aimed at understanding the enhancement mechanism of fluorescence intensity in presence of gold nanoparticles to utilize it in molecular sensing and in situ imaging in the microfluidic lab-on-chip device. Related phenomena are studied in situ in a microfluidic channel via fluorescence imaging. Detailed analysis is carried out to understand the possible mechanism of enhancement of fluorescence due to nanoparticles. In the present experimental study we show that SYTO9 fluorescence intensity increased in presence of Au nanoparticles of similar to 20 nm diameter. The fluorescence intensity is 20 time more compared to that in absence of Au nanoparticles. The enhancement of fluorescence intensity is attributed to the plasmonic resonance of Au nanoparticle at around the fluorescence emission wavelength. Underlying fundamental mechanism via dipole interaction model is explored for quantitative correlation of plasmonic enhancement properties.

AN INVESTIGATION OF CUTTING MECHANISMS AND STRAIN FIELDS DURING ORTHOGONAL CUTTING IN CFRPs

Fiber-reinforced plastics (FRPs) are typically difficult to machine due to their highly heterogeneous and anisotropic nature and the presence of two phases (fiber and matrix) with vastly different strengths and stiffnesses. Typical machining damage mechanisms in FRPs include series of brittle fractures (especially for thermosets) due to shearing and cracking of matrix material, fiber pull-outs, burring, fuzzing, fiber-matrix debonding, etc. With the aim of understanding the influence of the pronounced heterogeneity and anisotropy observed in FRPs, ``Idealized'' Carbon FRP (I-CFRP) plates were prepared using epoxy resin with embedded equispaced tows of carbon fibers. Orthogonal cutting of these I-CFRPs was carried out, and the chip formation characteristics, cutting force signals and strain distributions obtained during machining were analyzed using the Digital Image Correlation (DIC) technique. In addition, the same procedure was repeated on Uni-Directional CFRPs (UD-CFRPs). Chip formation mechanisms in FRPs were found to depend on the depth of cut and fiber orientation with pure epoxy showing a pronounced ``size effect.'' Experimental results indicate that in-situ full field strain measurements from DIC coupled with force measurements using dynamometry provide an adequate measure of anisotropy and heterogeneity during orthogonal cutting.

Insight into the Evaporation Dynamics of a Pair of Sessile Droplets on a Hydrophobic Substrate

In this work, we have demonstrated three unique regimes in the evaporation lifecycle of a pair of sessile droplets placed in variable proximity on a hydrophobic substrate. For small separation distance, the droplets undergo asymmetric spatiotemporal,evaporation leading to contact angle hysteresis and suppressed vaporization. The reduced evaporation has been attributed quantitatively to the existence of a constrained vapor-rich dome between the two droplets. However, a dynamic decrease in the droplet radius due to solvent removal marks a return to symmetry in terms of evaporation and contact angle. We have described the variation in evaporation flux using a universal correction factor. We have also demonstrated the existence of a critical separation distance beyond which the droplets in the, droplet pair do not affect each other. The results are crucial to a plethora of applications ranging from surface patterning to lab-on-a-chip devices.

Insight into the Evaporation Dynamics of a Pair of Sessile Droplets on a Hydrophobic Substrate

In this work, we have demonstrated three unique regimes in the evaporation lifecycle of a pair of sessile droplets placed in variable proximity on a hydrophobic substrate. For small separation distance, the droplets undergo asymmetric spatiotemporal,evaporation leading to contact angle hysteresis and suppressed vaporization. The reduced evaporation has been attributed quantitatively to the existence of a constrained vapor-rich dome between the two droplets. However, a dynamic decrease in the droplet radius due to solvent removal marks a return to symmetry in terms of evaporation and contact angle. We have described the variation in evaporation flux using a universal correction factor. We have also demonstrated the existence of a critical separation distance beyond which the droplets in the, droplet pair do not affect each other. The results are crucial to a plethora of applications ranging from surface patterning to lab-on-a-chip devices.

Fabrication and Nonlinear Thermomechanical Analysis of SU8 Thermal Actuator

SU8-based micromechanical structures are widely used as thermal actuators in the development of compliant micromanipulation tools. This paper reports the design, nonlinear thermomechanical analysis, fabrication, and thermal actuation of SU8 actuators. The thermomechanical analysis of the actuator incorporates nonlinear temperature-dependent properties of SU8 polymer to accurately model its thermal response during actuation. The designed SU8 thermal actuators are fabricated using surface micromachining techniques and the electrical interconnects are made to them using flip-chip bonding. The issues due to thermal stress during fabrication are discussed and a novel strategy is proposed to release the thermal stress in the fabricated actuators. Subsequent characterization of the actuator using an optical profilometer reveals excellent thermal response, good repeatability, and low hysteresis. The average deflection is similar to 8.5 mu m for an actuation current of similar to 5 mA. The experimentally obtained deflection profile and the tip deflection at different currents are both shown to be in good agreement with the predictions of the nonlinear thermomechanical model. This underscores the need to consider nonlinearities when modeling the response of SU8 thermal actuators. 2015-0087]

A Label-Free Multisensing Immunosensor Based on Imaging Ellipsometry

An immunosensor based on imaging ellipsometry and its potential applications was demonstrated in this paper. It has been proven a fast, reliable, and convenient method to quantify the thickness distribution of protein layers or detect protein concentration in solution. Combined with a protein chip, the immunosensor was able to detect multiple analytes simultaneously without any labeling. Preliminary results demonstrated how this immunosensor could be used to monitor several independent biospecific binding processes in real-time and in situ conditions.

Feasibility of Protein a for the Oriented Immobilization of Immunoglobulin on Silicon Surface for a Biosensor with Imaging Ellipsometry

The feasibility of using protein A to immobilize antibody on silicon surface for a biosensor with imaging ellipsometry was presented in this study. The amount of human IgG bound with anti-IgG immobilized by the protein A on silicon surface was much more than that bound with anti-IgG immobilized by physical adsorption. The result indicated that the protein A could be used to immobilize antibody molecules in a highly oriented manner and maintain antibody molecular functional configuration on the silicon surface. High reproducibility of the amount of antibody immobilization and homogenous antibody adsorption layer on surfaces could be obtained by this immobilization method. Imaging ellipsometry has been proven to be a fast and reliable detection method and sensitive enough to detect small changes in a molecular monolayer level. The combination of imaging ellipsometry and surface modification with protein A has the potential to be further developed into an efficient immunoassay protein chip.