Projecto de um conversor redutor CC-CC comutado para SoC

A evolução da tecnologia CMOS tem possibilitado uma maior densidade de integração de circuitos tornando possível o aumento da complexidade dos sistemas. No entanto, a integração de circuitos de gestão de potência continua ainda em estudo devido à dificuldade de integrar todos os componentes. Esta solução apresenta elevadas vantagens, especialmente em aplicações electrónicas portáteis alimentadas a baterias, onde a autonomia é das principais características. No âmbito dos conversores redutores existem várias topologias de circuitos que são estudadas na área de integração. Na categoria dos conversores lineares utiliza-se o LDO (Low Dropout Regulator), apresentando no entanto baixa eficiência para relações de conversão elevadas. Os conversores comutados são elaborados através do recurso a circuitos de comutação abrupta, em que a eficiência deste tipo de conversores não depende do rácio de transformação entre a tensão de entrada e a de saída. A diminuição física dos processos CMOS tem como consequência a redução da tensão máxima que os transístores suportam, impondo o estudo de soluções tolerantes a “altatensão”, com o intuito de manter compatibilidade com tensões superiores que existam na placa onde o circuito é incluído. Os sistemas de gestão de energia são os primeiros a acompanhar esta evolução, tendo de estar aptos a fornecer a tensão que os restantes circuitos requerem. Neste trabalho é abordada uma metodologia de projecto para conversores redutores CCCC comutados em tecnologia CMOS, tendo-se maximizado a frequência com vista à integração dos componentes de filtragem em circuito integrado. A metodologia incide sobre a optimização das perdas totais inerentes à comutação e condução, dos transístores de potência e respectivos circuitos auxiliares. É apresentada uma nova metodologia para o desenvolvimento de conversores tolerantes a “alta-tensão”.

Laser-assisted deposition of thin films from photoexcited vapour phases

Laser-assisted chemical vapour deposition (LCVD) has been extensively studied in the last two decades. A vast range of applications encompass various areas such as microelectronics, micromechanics, microelectromechanics and integrated optics, and a variety of metals, semiconductors and insulators have been grown by LCVD. In this article, we review briefly the LCVD process and present two case studies of thin film deposition related to laser thermal excitation (e.g., boron carbide) and non-thermal excitation (e.g., CrO(2)) of the gas phase.

A Voltage Limiter Circuit for Indoor Light Energy Harvesting Applications

A voltage limiter circuit for indoor light energy harvesting applications is presented. This circuit is a part of a bigger system, whose function is to harvest indoor light energy, process it and store it, so that it can be used at a later time. This processing consists on maximum power point tracking (MPPT) and stepping-up, of the voltage from the photovoltaic (PV) harvester cell. The circuit here described, ensures that even under strong illumination, the generated voltage will not exceed the limit allowed by the technology, avoiding the degradation, or destruction, of the integrated die. A prototype of the limiter circuit was designed in a 130 nm CMOS technology. The layout of the circuit has a total area of 23414 mu m(2). Simulation results, using Spectre, are presented.

A 5GHz1.8V Low Power CMOS Low-Noise Amplifier

Wireless local-area networks (WLANs) have been deployed as office and home communications infrastructures worldwide. The diversification of the standards, such as IEEE 802.11 series demands the design of RF front-ends. Low power consumption is one of the most important design concerns in the application of those technologies. To maintain competitive hardware costs, CMOS has been used since it is the best solution for low cost and high integration processing, allowing analog circuits to be mixed with digital ones. In the receiver chain, the low noise amplifier (LNA) is one of the most critical blocks in a transceiver design. The sensitivity is mainly determined by the LNA noise figure and gain. It interfaces with the pre-select filter and the mixer. Furthermore, since it is the first gain stage, care must be taken to provide accurate input match, low-noise figure, good linearity and a sufficient gain over a wide band of operation. Several CMOS LNAs have been reported during the last decade, showing that the most research has been done at 802.11/b and GSM standards (900-2400MHz spectrum) and more recently at 802.11/a (5GHz band). One of the more significant disadvantages of 802.11/b is that the frequency band is crowded and subject to interference from other technologies, as is 2.4GHz cordless phones and Bluetooth. As the demand for radio-frequency integrated circuits, operating at higher frequency bands, increases, the IEEE 802.11/a standard becomes a very attractive option to wireless communication system developers. This paper presents the design and implementation of a low power, low noise amplifier aimed at IEEE 802.11a for WLAN applications. It was designed to be integrated with an active balun and mixer, representing the first step toward a fully integrated monolithic WLAN receiver. All the required circuits are integrated at the same die and are powered by 1.8V supply source. Preliminary experimental results (S-parameters) are shown and promise excellent results. The LNA circuit design details are illustrated in Section 2. Spectre simulation results focused at gain, noise figure (NF) and input/output matching are presented in Section 3. Finally, conclusions and comparison with other recently reported LNAs are made in Section 4, followed by future work.

Controlador Boundary-Scan

A crescente complexidade dos sistemas electrónicos associada a um desenvolvimento nas tecnologias de encapsulamento levou à miniaturização dos circuitos integrados, provocando dificuldades e limitações no diagnóstico e detecção de falhas, diminuindo drasticamente a aplicabilidade dos equipamentos ICT. Como forma de lidar com este problema surgiu a infra-estrutura Boundary Scan descrita na norma IEEE1149.1 “Test Access Port and Boundary-Scan Architecture”, aprovada em 1990. Sendo esta solução tecnicamente viável e interessante economicamente para o diagnóstico de defeitos, efectua também outras aplicações. O SVF surgiu do desejo de incutir e fazer com que os fornecedores independentes incluíssem a norma IEEE 1149.1, é desenvolvido num formato ASCII, com o objectivo de enviar sinais, aguardar pela sua resposta, segundo a máscara de dados baseada na norma IEEE1149.1. Actualmente a incorporação do Boundary Scan nos circuitos integrados está em grande expansão e consequentemente usufrui de uma forte implementação no mercado. Neste contexto o objectivo da dissertação é o desenvolvimento de um controlador boundary scan que implemente uma interface com o PC e possibilite o controlo e monitorização da aplicação de teste ao PCB. A arquitectura do controlador desenvolvido contém um módulo de Memória de entrada, um Controlador TAP e uma Memória de saída. A implementação do controlador foi feita através da utilização de uma FPGA, é um dispositivo lógico reconfiguráveis constituído por blocos lógicos e por uma rede de interligações, ambos configuráveis, que permitem ao utilizador implementar as mais variadas funções digitais. A utilização de uma FPGA tem a vantagem de permitir a versatilidade do controlador, facilidade na alteração do seu código e possibilidade de inserir mais controladores dentro da FPGA. Foi desenvolvido o protocolo de comunicação e sincronização entre os vários módulos, permitindo o controlo e monitorização dos estímulos enviados e recebidos ao PCB, executados automaticamente através do software do Controlador TAP e de acordo com a norma IEEE 1149.1. A solução proposta foi validada por simulação utilizando o simulador da Xilinx. Foram analisados todos os sinais que constituem o controlador e verificado o correcto funcionamento de todos os seus módulos. Esta solução executa todas as sequências pretendidas e necessárias (envio de estímulos) à realização dos testes ao PCB. Recebe e armazena os dados obtidos, enviando-os posteriormente para a memória de saída. A execução do trabalho permitiu concluir que os projectos de componentes electrónicos tenderão a ser descritos num nível de abstracção mais elevado, recorrendo cada vez mais ao uso de linguagens de hardware, no qual o VHDL é uma excelente ferramenta de programação. O controlador desenvolvido será uma ferramenta bastante útil e versátil para o teste de PCBs e outras funcionalidades disponibilizadas pelas infra-estruturas BS.

Multiresidue pesticides analysis in soils using modified QuEChERS with disposable pipette extraction and dispersive solid-phase extraction

QuEChERS original method was modified into a new version for pesticides determination in soils. The QuEChERS method is based on liquid–liquid portioning with ACN and was followed by cleanup step using dispersive SPE and disposable pipette tips. Gas chromatographic separation with MS detection was carried out for pesticides quantification. The method was validated using recovery experiments for 36 multiclass pesticides. Mean recoveries of pesticides at each of the four spiking levels between 10–300 µg/kg of soil ranged from 70–120% for 26 pesticides with RSD values less than 15%. The method achieved low limit of detection less than 7.6 µ g/kg. Matrix effects were observed for 13 pesticides. Matrix effects were compensated by using matrix-matched calibration. The method was applied successfully using d-SPE or DPX in the analysis of the pesticides in soils from organic farming and integrated pest management.

Sistema de reconhecimento de impressões digitais baseado em FPGA

Trabalho de Projeto para obtenção do grau de Mestre em Engenharia de Eletrónica e Telecomunicações

Melhoria da eficiência de amplificadores de potência para sinais RF com envolvente variável

Trabalho Final de Mestrado para obtenção do grau de Mestre em Engenharia Electrónica e Telecomunicações

A CMOS micro power switched-capacitor DC-DC step-up converter for indoor light energy harvesting applications

This paper presents a micro power light energy harvesting system for indoor environments. Light energy is collected by amorphous silicon photovoltaic (a-Si:H PV) cells, processed by a switched capacitor (SC) voltage doubler circuit with maximum power point tracking (MPPT), and finally stored in a large capacitor. The MPPT fractional open circuit voltage (V-OC) technique is implemented by an asynchronous state machine (ASM) that creates and dynamically adjusts the clock frequency of the step-up SC circuit, matching the input impedance of the SC circuit to the maximum power point condition of the PV cells. The ASM has a separate local power supply to make it robust against load variations. In order to reduce the area occupied by the SC circuit, while maintaining an acceptable efficiency value, the SC circuit uses MOSFET capacitors with a charge sharing scheme for the bottom plate parasitic capacitors. The circuit occupies an area of 0.31 mm(2) in a 130 nm CMOS technology. The system was designed in order to work under realistic indoor light intensities. Experimental results show that the proposed system, using PV cells with an area of 14 cm(2), is capable of starting-up from a 0 V condition, with an irradiance of only 0.32 W/m(2). After starting-up, the system requires an irradiance of only 0.18 W/m(2) (18 mu W/cm(2)) to remain operating. The ASM circuit can operate correctly using a local power supply voltage of 453 mV, dissipating only 0.085 mu W. These values are, to the best of the authors' knowledge, the lowest reported in the literature. The maximum efficiency of the SC converter is 70.3 % for an input power of 48 mu W, which is comparable with reported values from circuits operating at similar power levels.

ROM-less RNS-to-binary converter moduli {22N − 1, 22N + 1, 2N − 3, 2N + 3}

In this paper, a novel ROM-less RNS-to-binary converter is proposed, using a new balanced moduli set {22n-1, 22n + 1, 2n-3, 2n + 3} for n even. The proposed converter is implemented with a two stage ROM-less approach, which computes the value of X based only in arithmetic operations, without using lookup tables. Experimental results for 24 to 120 bits of Dynamic Range, show that the proposed converter structure allows a balanced system with 20% faster arithmetic channels regarding the related state of the art, while requiring similar area resources. This improvement in the channel's performance is enough to offset the higher conversion costs of the proposed converter. Furthermore, up to 20% better Power-Delay-Product efficiency metric can be achieved for the full RNS architecture using the proposed moduli set. © 2014 IEEE.

VISIR: experiences and challenges

It is of crucial importance the integration of practical sessions in engineering curricula owing to their significant role in understanding engineering concepts and scientific phenomena. However, the lack of practical sessions due to the high costs of the equipment and the unavailability of instructors has caused a significant declination in experimentation in engineering education. Remote laboratories have tackled this issues providing online reusable and shared workbenches unconstrained by neither geographical nor time considerations. Thereby, they have extremely proliferated among universities and integrated into engineering curricula over the last decade. This contribution compiles diverse experiences based on the deployment of the remote laboratory, Virtual Instrument Systems in Reality (VISIR), on the practices of undergraduate engineering grades at various universities within the VISIR community. It aims to show the impact of its usage on engineering education concerning the assessments of students and teachers as well. In addition, the paper address the next challenges and future works carried out at several universities within the VISIR community.

Liquid crystal beads constrained on thin cellulosic fibers: Electric field induced microrotors and N-I transition

We directly visualize the response of nematic liquid crystal drops of toroidal topology threaded in cellulosic fibers, suspended in air, to an AC electric field and at different temperatures over the N-I transition. This new liquid crystal system can exhibit non-trivial point defects, which can be energetically unstable against expanding into ring defects depending on the fiber constraining geometries. The director anchoring tangentially near the fiber surface and homeotropically at the air interface makes a hybrid shell distribution that in turn causes a ring disclination line around the main axis of the fiber at the center of the droplet. Upon application of an electric field, E, the disclination ring first expands and moves along the fiber main axis, followed by the appearance of a stable "spherical particle" object orbiting around the fiber at the center of the liquid crystal drop. The rotation speed of this particle was found to vary linearly with the applied voltage. This constrained liquid crystal geometry seems to meet the essential requirements in which soliton-like deformations can develop and exhibit stable orbiting in three dimensions upon application of an external electric field. On changing the temperature the system remains stable and allows the study of the defect evolution near the nematic-isotropic transition, showing qualitatively different behaviour on cooling and heating processes. The necklaces of such liquid crystal drops constitute excellent systems for the study of topological defects and their evolution and open new perspectives for application in microelectronics and photonics.

Innovative manufacturing process for hybrid pultruded products based on cork and polymeric pre-shapes

Pultruded products are being targeted by a growing demand due to its excellent mechanical properties and low chemical reactivity, ensuring a low level of maintenance operations and allowing an easier assembly operation process than equivalent steel bars. In order to improve the mechanical drawing process and solve some acoustic and thermal insulation problems, pultruded pipes of glass fibre reinforced plastics (GFRF) can be filled with special products that increase their performance regarding the issues previously referred. The great challenge of this work was drawing a new equipment able to produce pultruded pipes filled with cork or polymeric pre-shaped bars as a continuous process. The project was carried out successfully and the new equipment was built and integrated in the pultrusion equipment already existing, allowing to obtain news products with higher added-value in the market, covering some needs previously identified in the field of civil construction.

Integrated Management of IaaS Resources

This paper proposes and reports the development of an open source solution for the integrated management of Infrastructure as a Service (IaaS) cloud computing resources, through the use of a common API taxonomy, to incorporate open source and proprietary platforms. This research included two surveys on open source IaaS platforms (OpenNebula, OpenStack and CloudStack) and a proprietary platform (Parallels Automation for Cloud Infrastructure - PACI) as well as on IaaS abstraction solutions (jClouds, Libcloud and Deltacloud), followed by a thorough comparison to determine the best approach. The adopted implementation reuses the Apache Deltacloud open source abstraction framework, which relies on the development of software driver modules to interface with different IaaS platforms, and involved the development of a new Deltacloud driver for PACI. The resulting interoperable solution successfully incorporates OpenNebula, OpenStack (reuses pre-existing drivers) and PACI (includes the developed Deltacloud PACI driver) nodes and provides a Web dashboard and a Representational State Transfer (REST) interface library. The results of the exchanged data payload and time response tests performed are presented and discussed. The conclusions show that open source abstraction tools like Deltacloud allow the modular and integrated management of IaaS platforms (open source and proprietary), introduce relevant time and negligible data overheads and, as a result, can be adopted by Small and Medium-sized Enterprise (SME) cloud providers to circumvent the vendor lock-in problem whenever service response time is not critical.

Energy evaporation: the new concept of indoor systems for WPT and EH embedded into the floor

This work introduces a novel idea for wireless energy transfer, proposing for the first time the unit-cell of an indoor localization and RF harvesting system embedded into the floor. The unit-cell is composed by a 5.8 GHz patch antenna surrounded by a 13.56 MHz coil. The coil locates a device and activate the patch which, connected to a power grid, radiates to wirelessly charge the localized device. The HF and RF circuits co-existence and functionality are demonstrated in this paper, the novelty of which is also in the adoption of low cost and most of all ecofriendly materials, such as wood and cork, as substrates for electronics.