Coupling of High Voltage AC Power Line Fields to Metallic Pipelines

In the recent years, there has been a trend to run metallic pipelines carrying petroleum products and high voltage AC power lines parallel to each other in a relatively narrow strip of land. Due to this sharing of the right-of-way, verhead AC power line electric field may induce voltages on the metallic pipelines running in close vicinity leading to serious adverse effects. In this paper, the induced voltages on metallic pipelines running in close vicinity of high voltage power transmission lines have been computed. Before computing the induced voltages, an optimum configuration of the phase conductors based on the lowest conductor surface gradient and field under transmission line has been arrived at. This paper reports the conductor surface field gradients calculated for the various configurations. Also the electric fields under transmission line, for single circuit and double circuit (various phase arrangements) have been analyzed. Based on the above results, an optimum configuration giving the lowest field under the power line as well as the lowest conductor surface gradient has been arrived at and for this configuration, induced voltage on the pipeline has been computed using the Charge Simulation Method (CSM). For comparison, induced voltages on the pipeline has been computed for the various other phase configurations also.

Voltage and Temperature-Aware SSTA Using Neural Network Delay Model

With the emergence of voltage scaling as one of the most powerful power reduction techniques, it has been important to support voltage scalable statistical static timing analysis (SSTA) in deep submicrometer process nodes. In this paper, we propose a single delay model of logic gate using neural network which comprehensively captures process, voltage, and temperature variation along with input slew and output load. The number of simulation programs with integrated circuit emphasis (SPICE) required to create this model over a large voltage and temperature range is found to be modest and 4x less than that required for a conventional table-based approach with comparable accuracy. We show how the model can be used to derive sensitivities required for linear SSTA for an arbitrary voltage and temperature. Our experimentation on ISCAS 85 benchmarks across a voltage range of 0.9-1.1V shows that the average error in mean delay is less than 1.08% and average error in standard deviation is less than 2.85%. The errors in predicting the 99% and 1% probability point are 1.31% and 1%, respectively, with respect to SPICE. The two potential applications of voltage-aware SSTA have been presented, i.e., one for improving the accuracy of timing analysis by considering instance-specific voltage drops in power grids and the other for determining optimum supply voltage for target yield for dynamic voltage scaling applications.

Insulating State and Breakdown of Fermi Liquid Description in Molecular-Scale Single-Crystalline Wires of Gold

Electrical transport measurements on ultrathin single-crystalline Au nanowires, synthesized via a wet chemical route, show an unexpected insulating behavior. The linear response electrical resistance exhibits a power-law dependence on temperature. In addition, the variation of current over a wide range of temperature and voltage obeys a universal scaling relation that provides compelling evidence for a non-Fermi liquid behavior. Our results demonstrate that the quantum ground state In ultrathin nanowires of simple metallic systems can be radically different from their bulk counterparts and can be described In terms of a Tomonaga-Luttinger liquid (TLL), in the presence of remarkably strong electron-electron interactions.

Anomalous temperature dependence of phonons and photoluminescence bands in pyrochlore Er(2)Ti(2)O(7): signatures of structural deformation at 130 K

We report a Raman study of single crystal pyrochlore Er(2)Ti(2)O(7) as a function of temperature from 12 to 300 K. In addition to the phonons, various photoluminescence (PL) lines of Er(3+) in the visible range are also observed. Our Raman data show an anomalous red-shift of two phonons (one at similar to 200 cm(-1) and another at similar to 520 cm(-1)) upon cooling from room temperature which is attributed to phonon-phonon anharmonic interactions. However, the phonons at similar to 310, 330, and 690 cm(-1) initially show a blue-shift upon cooling from room temperature down to about 130 K, followed by a red-shift, indicating a structural deformation at similar to 130 K. The intensities of the PL bands associated with the transitions between the various levels of the ground state manifold ((4)I(15/2)) and the (2)H(11/2) as well as (4)S(3/2) excited state manifolds of Er(3+) show a change at similar to 130 K. Moreover, the temperature dependence of the peak position of the two PL bands shows a change in their slope (d(omega)/d(T)) at similar to 130 K, thus further strengthening the proposal of a structural deformation. The temperature dependence of the peak positions of the PL bands has been analyzed using the theory of optical dephasing in crystals.

Effect of substrate bias voltage on the structure, electric and dielectric properties of TiO(2) thin films by DC magnetron sputtering

Titanium dioxide (TiO(2)) films have been deposited on glass and p-silicon (1 0 0) substrates by DC magnetron sputtering technique to investigate their structural, electrical and optical properties. The surface composition of the TiO(2) films has been analyzed by X-ray photoelectron spectroscopy. The TiO(2) films formed on unbiased substrates were amorphous. Application of negative bias voltage to the substrate transformed the amorphous TiO(2) into polycrystalline as confirmed by Raman spectroscopic studies. Thin film capacitors with configuration of Al/TiO(2)/p-Si have been fabricated. The leakage current density of unbiased films was 1 x10(-6) A/cm(2) at a gate bias voltage of 1.5 V and it was decreased to 1.41 x 10(-7) A/cm(2) with the increase of substrate bias voltage to -150 V owing to the increase in thickness of interfacial layer of SiO(2). Dielectric properties and AC electrical conductivity of the films were studied at various frequencies for unbiased and biased at -150 V. The capacitance at 1 MHz for unbiased films was 2.42 x 10(-10) F and it increased to 5.8 x 10(-10) F in the films formed at substrate bias voltage of -150 V. Dielectric constant of TiO(2) films were calculated from capacitance-voltage measurements at 1 MHz frequency. The dielectric constant of unbiased films was 6.2 while those formed at -150 V it increased to 19. The optical band gap of the films decreased from 3.50 to 3.42 eV with the increase of substrate bias voltage from 0 to -150 V. (C) 2011 Elsevier B. V. All rights reserved.

Dynamic Supply and Threshold Voltage Scaling for CMOS Digital Circuits Using In-Situ Power Monitor

A generalized power tracking algorithm that minimizes power consumption of digital circuits by dynamic control of supply voltage and the body bias is proposed. A direct power monitoring scheme is proposed that does not need any replica and hence can sense total power consumed by load circuit across process, voltage, and temperature corners. Design details and performance of power monitor and tracking algorithm are examined by a simulation framework developed using UMC 90-nm CMOS triple well process. The proposed algorithm with direct power monitor achieves a power savings of 42.2% for activity of 0.02 and 22.4% for activity of 0.04. Experimental results from test chip fabricated in AMS 350 nm process shows power savings of 46.3% and 65% for load circuit operating in super threshold and near sub-threshold region, respectively. Measured resolution of power monitor is around 0.25 mV and it has a power overhead of 2.2% of die power. Issues with loop convergence and design tradeoff for power monitor are also discussed in this paper.

Low‐voltage varistors based on zinc antimony spinel Zn7Sb2O12

It is possible to prepare low‐voltage varistors from the zinc antimony spinel Zn7Sb2O12 with breakdown voltages in the range of 3–20 V and nonlinearity coefficient α=7–15. The varistor property is due to the formation of high ohmic potential barriers at the grain boundary regions on low‐ohmic n‐type grain interiors of the polycrystalline samples. The method of preparation of the spinel, synthesized by coprecipitation followed by annealing under restricted partial pressures of oxygen, controls the mixed valence states for antimony, namely, Sb3+ and Sb5+. This is critical in attaining high nonlinearity and lower breakdown voltages.

Temperature dependence of the energy gap and free carrier absorption in bulk InAs0.05Sb0.95 single crystals

Temperature dependence of the energy gap and free carrier absorption in a high-quality InAs0.05Sb0.95 single crystal was studied between 90 K and 430 K through the absorption spectra. At this alloy concentration, the room-temperature energy gap was measured to be 0.15 eV. Varshni- and the Bose–Einstein-type fit parameters were obtained from the measured temperature dependence of the energy gap, and the latter gave the zero-temperature gap to be 0.214 eV. It was found that although Weider’s empirical formula for the dependence of the energy gap on temperature and the alloy concentration agrees with the value of the gap at room temperature, it is inaccurate in describing its temperature dependence. From the free carrier absorption measurements, the phonon limited cross section of 7.35×10−16 cm2 at 15 μm was deduced at room temperature.

A mostly-digital analog scan-out chain for low bandwidth voltage measurement for analog IP test

A method of precise measurement of on-chip analog voltages in a mostly-digital manner, with minimal overhead, is presented. A pair of clock signals is routed to the node of an analog voltage. This analog voltage controls the delay between this pair of clock signals, which is then measured in an all-digital manner using the technique of sub-sampling. This sub-sampling technique, having measurement time and accuracy trade-off, is well suited for low bandwidth signals. This concept is validated by designing delay cells, using current starved inverters in UMC 130nm CMOS process. Sub-mV accuracy is demonstrated for a measurement time of few seconds.

High voltage DC power supply topology for pulsed load applications with converter switching synchronized to load pulses

High voltage power supplies for radar applications are investigated, which are subjected to pulsed load (125 kHz and 10% duty cycle) with stringent specifications (<0.01% regulation, efficiency>85%, droop<0.5 V/micro-sec.). As good regulation and stable operation requires the converter to be switched at much higher frequency than the pulse load frequency, transformer poses serious problems of insulation failure and higher losses. This paper proposes a methodology to tackle the problems associated with this type of application. Synchronization of converter switching with load pulses enables the converter to switch at half the load switching frequency. Low switching frequency helps in ensuring safety of HV transformer insulation and reduction of losses due to skin and proximity effect. Phase-modulated series resonant converter with ZVS is used as the power converter.

Input voltage modulated high voltage DC power supply topology for pulsed load applications

High voltage power supplies for radar applications are investigated which are subjected to pulsed load with stringent specifications. In the proposed solution, power conversion is done in two stages. A low power-high frequency converter modulates the input voltage of a high power-low frequency converter. This method satisfies all the performance specifications and takes care of the critical aspects of HV transformer.

Low threshold voltage ZnO thin film transistor with a Zn0.7Mg0.3O gate dielectric for transparent electronics

A highly transparent all ZnO thin film transistor (ZnO-TFT) with a transmittance of above 80% in the visible part of the spectrum, was fabricated by direct current magnetron sputtering, with a bottom gate configuration. The ZnO-TFT with undoped ZnO channel layers deposited on 300 nm Zn0.7Mg0.3O gate dielectric layers attains an on/off ratio of 104 and mobility of 20 cm2/V s. The capacitance-voltage (C−V) characteristics of the ZnO-TFT exhibited a transition from depletion to accumulation with a small hysteresis indicating the presence of oxide traps. The trap density was also computed from the Levinson’s plot. The use of Zn0.7Mg0.3O as a dielectric layer adds additional dimension to its applications. The room temperature processing of the device depicts the possibility of the use of flexible substrates such as polymer substrates. The results provide the realization of transparent electronics for next-generation optoelectronics.