Design and realization of high-performance wave-pipelined 8×8 b multiplier in CMOS technology

Wave pipelining is a design technique for increasing the throughput of a digital circuit or system without introducing pipelining registers between adjacent combinational logic blocks in the circuit/system. However, this requires balancing of the delays along all the paths from the input to the output which comes the way of its implementation. Static CMOS is inherently susceptible to delay variation with input data, and hence, receives a low priority for wave pipelined digital design. On the other hand, ECL and CML, which are amenable to wave pipelining, lack the compactness and low power attributes of CMOS. In this paper we attempt to exploit wave pipelining in CMOS technology. We use a single generic building block in Normal Process Complementary Pass Transistor Logic (NPCPL), modeled after CPL, to achieve equal delay along all the propagation paths in the logic structure. An 8×8 b multiplier is designed using this logic in a 0.8 ?m technology. The carry-save multiplier architecture is modified suitably to support wave pipelining, viz., the logic depth of all the paths are made identical. The 1 mm×0.6 mm multiplier core supports a throughput of 400 MHz and dissipates a total power of 0.6 W. We develop simple enhancements to the NPCPL building blocks that allow the multiplier to sustain throughputs in excess of 600 MHz. The methodology can be extended to introduce wave pipelining in other circuits as well

Multifunctional cryogenic sensors from n-BaTiO3 ceramics having strong negative temperature coefficient of resistance

Donor-doped n-BaTiO3 polycrystalline ceramics show a strong negative temperature coefficient of resistivity below the orthorhombic-rhombohedral phase transition point, from 10(2-3) Omega cm af 190 K to 10(10-13) Omega cm at less than or similar to 50 K, with thermal coefficient of resistance alpha = 20-23% K-1. Stable thermal sensors for low-temperature applications are realized therefrom. The negative temperature coefficient of resistivity region can be modified by substituting isovalent ions in the lattice. Highly nonlinear current-voltage (I-V) curves are observed at low temperatures, with a voltage maximum followed by the negative differential resistance. The I-V curves are sensitive to dissipation so that cryogenic sensors can be fabricated for liquid level control, flow rate monitoring, radiation detection or in-rush voltage limitation.

Graphics Processing Units for the Real-time Linear Elastostatic Simulation of Liver

Biomedical engineering solutions like surgical simulators need High Performance Computing (HPC) to achieve real-time performance. Graphics Processing Units (GPUs) offer HPC capabilities at low cost and low power consumption. In this work, it is demonstrated that a liver which is discretized by about 2500 finite element nodes, can be graphically simulated in realtime, by making use of a GPU. Present work takes into consideration the time needed for the data transfer from CPU to GPU and back from GPU to CPU. Although behaviour of liver is very complicated, present computer simulation assumes linear elastostatics. One needs to use the commercial software ANSYS to obtain the global stiffness matrix of the liver. Results show that GPUs are useful for the real-time graphical simulation of liver, which in turn is needed in simulators that are used for training surgeons in laparoscopic surgery. Although the computer simulation should involve rendering also, neither rendering, nor the time needed for rendering and displaying the liver on a screen, is considered in the present work. The present work is just a demonstration of a concept; the concept is not really implemented and validated. Future work is to develop software which can accomplish real-time and very realistic graphical simulation of liver, with rendered image of liver on the screen changing in real-time according to the position of the surgical tool tip approximated as the mouse cursor in 3D.

Localisation of discrete change in a transformer winding: a network-function-loci approach

An entirely different approach for localisation of winding deformation based on terminal measurements is presented. Within the context of this study, winding deformation means, a discrete and specific change externally imposed at a particular position on the winding. The proposed method is based on pre-computing and plotting the complex network-function loci e.g. driving-point impedance (DPI)] at a selected frequency, for a meaningful range of values for each element (increasing and decreasing) of the ladder network which represents the winding. This loci diagram is called the nomogram. After introducing a discrete change, amplitude and phase of DPI are measured. By plotting this single measurement on the nomogram, it is possible to estimate the location and identify the extent of change. In contrast to the existing approach, the proposed method is fast, non-iterative and yields reasonably good localisation. Experimental results for actual transformer windings (interleaved and continuous disc) are presented.

A Novel VSI- and CSI-Fed Active-Reactive Induction Motor Drive with Sinusoidal Voltages and Currents

Till date load-commutated inverter (LCI)-fed synchronous motor drive configuration is popular in high power applications (>10 MW). The leading power factor operation of synchronous motor by excitation control offers this simple and rugged drive structure. On the contrary, LCI-fed induction motor drive is absent as it always draws lagging power factor current. Therefore, complicated commutation circuit is required to switch off thyristors for a current source inverter (CSI)-driven induction motor. It poses the major hindrance to scale up the power rating of CSI-fed induction motor drive. Anew power topology for LCI-fed induction motor drive for medium-voltage drive application is proposed. A new induction machine (active-reactive induction machine) with two sets of three-phase winding is introduced as a drive motor. The proposed power configuration ensures sinusoidal voltage and current at the motor terminals. The total drive power is shared among a thyristor-based LCI, an insulated gate bipolar transistor (IGBT)-based two-level voltage source inverter (VSI), and a three-level VSI. The benefits of SCRs and IGBTs are explored in the proposed drive. Experimental results from a prototype drive verify the basic concepts of the drive.

Wireless sensor networks forhuman intruder detection

In this paper we report on the outcomes of a research and demonstration project on human intrusion detection in a large secure space using an ad hoc wireless sensor network. This project has been a unique experience in collaborative research, involving ten investigators (with expertise in areas such as sensors, circuits, computer systems,communication and networking, signal processing and security) to execute a large funded project that spanned three to four years. In this paper we report on the specific engineering solution that was developed: the various architectural choices and the associated specific designs. In addition to developing a demonstrable system, the various problems that arose have given rise to a large amount of basic research in areas such as geographical packet routing, distributed statistical detection, sensors and associated circuits, a low power adaptive micro-radio, and power optimising embedded systems software. We provide an overview of the research results obtained.

Radio-Optical Imaging of ATLBS Survey

We present the radio-optical imaging of ATLBS, a sensitive radio survey (Subrahmanyan et al. 2010). The primary aim of the ATLBS survey is to image low-power radio sources which form the bulk of the radio source population to moderately high red-shifts (z similar to 1.0). The accompanying multiband optical and near infra-red observations provide information about the hosts and environments of the radio sources. We give here details of the imaging of the radio data and optical data for the ATLBS survey.

Five-level inverter voltage-space phasor generation for an open-end winding induction motor drive

A topology for voltage-space phasor generation equivalent to a five-level inverter for an open-end winding induction motor is presented. The open-end winding induction motor is fed from both ends by two three-level inverters. The three-level inverters are realised by cascading two two-level inverters. This inverter scheme does not experience neutral-point fluctuations. Of the two three-level inverters only one will be switching at any instant in the lower speed ranges. In the multilevel carrier-based SPWM used for the proposed drive, a progressive discrete DC bias depending on the speed range is given to the reference wave to reduce the inverter switchings. The drive is implemented and tested with a 1 HP open-end winding induction motor and experimental results are presented.

Construction of equivalent circuit of a transformer winding from driving-point impedance function - analytical approach

Analytical solution is presented to convert a given driving-point impedance function (in s-domain) into a physically realisable ladder network with inductive coupling between any two sections and losses considered. The number of sections in the ladder network can vary, but its topology is assumed fixed. A study of the coefficients of the numerator and denominator polynomials of the driving-point impedance function of the ladder network, for increasing number of sections, led to the identification of certain coefficients, which exhibit very special properties. Generalised expressions for these specific coefficients have also been derived. Exploiting their properties, it is demonstrated that the synthesis method essentially turns out to be an exercise of solving a set of linear, simultaneous, algebraic equations, whose solution directly yields the ladder network elements. The proposed solution is novel, simple and guarantees a unique network. Presently, the formulation can synthesise a unique ladder network up to six sections.

Adaptation of small capacity natural gas engine for producer gas operation

This article addresses the adaptation of a low-power natural gas engine for using producer gas as a fuel. The 5.9 L natural gas engine with a compression ratio of 10.5:1, rated at 55 kW shaft power, delivered 30 kW using producer gas as fuel in the naturally aspirated mode. Optimal ignition timing for peak power was found to be 20 degrees before top dead centre. Air-to-fuel ratio (A/F) was found to be 1.2 +/- 0.1 over a range of loads. Critical evaluation of the energy flows in the engine resulted in identifying losses and optimizing the engine cooling. The specific fuel consumption was found to be 1.2 +/- 0.1 kg of biomass per kilowatt hour. A reduction of 40 per cent in brake mean effective pressure was observed compared with natural gas operation. Governor response to load variations has been studied with respect to frequency recovery time. The study also attempts to adopt a turbocharger for higher power output. Preliminary results suggest a possibility of about 30 per cent increase in the output.

Compiler-assisted energy optimization for clustered VLIW processors

Clustered architecture processors are preferred for embedded systems because centralized register file architectures scale poorly in terms of clock rate, chip area, and power consumption. Although clustering helps by improving the clock speed, reducing the energy consumption of the logic, and making the design simpler, it introduces extra overheads by way of inter-cluster communication. This communication happens over long global wires having high load capacitance which leads to delay in execution and significantly high energy consumption. Inter-cluster communication also introduces many short idle cycles, thereby significantly increasing the overall leakage energy consumption in the functional units. The trend towards miniaturization of devices (and associated reduction in threshold voltage) makes energy consumption in interconnects and functional units even worse, and limits the usability of clustered architectures in smaller technologies. However, technological advancements now permit the design of interconnects and functional units with varying performance and power modes. In this paper, we propose scheduling algorithms that aggregate the scheduling slack of instructions and communication slack of data values to exploit the low-power modes of functional units and interconnects. Finally, we present a synergistic combination of these algorithms that simultaneously saves energy in functional units and interconnects to improves the usability of clustered architectures by achieving better overall energy-performance trade-offs. Even with conservative estimates of the contribution of the functional units and interconnects to the overall processor energy consumption, the proposed combined scheme obtains on average 8% and 10% improvement in overall energy-delay product with 3.5% and 2% performance degradation for a 2-clustered and a 4-clustered machine, respectively. We present a detailed experimental evaluation of the proposed schemes. Our test bed uses the Trimaran compiler infrastructure. (C) 2012 Elsevier Inc. All rights reserved.

Evaluation of carbon dioxide blends with isopentane and propane as working fluids for organic Rankine cycles

The main theme of this paper is to study the flammability suppression of hydrocarbons by blending with carbon dioxide, and to evaluate these mixtures as possible working fluids in organic Rankine cycle for medium temperature concentrated solar power applications. The analysis takes into account inevitable irreversibilities in the turbine, the pump, and heat exchangers. While the isopentane + CO2 mixture suffers from high irreversibility mainly in the regenerator owing to a large temperature glide, the propane + CO2 mixture performs more or less the same as pure propane albeit with high cycle pressures. In general, large temperature glides at condensing pressures extend the heat recovery into the two-phase dome, which is an advantage. However, at the same time, the shift of the pinch point towards the warm end of the regenerator is found to be a major cause of irreversibility. In fact, as the number of carbon atoms in alkanes decreases, their blend with CO2 moves the pinch point to the colder end of the regenerator. This results in lower entropy generation in the regenerator and improved cycle efficiency of propane + CO2 mixtures. With this mixture, real cycle efficiencies of 15-18% are achievable at a moderate source temperature of 573 K. Applicability for a wide range of source temperatures is found to be an added advantage of this mixture.

A tuned rectifier for RF energy harvesting from ambient radiations

A circuit topology based on accumulate-and-use philosophy has been developed to harvest RF energy from ambient radiations such as those from cellular towers. Main functional units of this system are antenna, tuned rectifier, supercapacitor, a gated boost converter and the necessary power management circuits. Various RF aspects of the design philosophy for maximizing the conversion efficiency at an input power level of 15 mu W are presented here. The system is characterized in an anechoic chamber and it has been established that this topology can harvest RF power densities as low as 180 mu W/m(2) and can adaptively operate the load depending on the incident radiation levels. The output of this system can be easily configured at a desired voltage in the range 2.2-4.5 V. A practical CMOS load - a low power wireless radio module has been demonstrated to operate intermittently by this approach. This topology can be easily modified for driving other practical loads, from harvested RF energy at different frequencies and power levels.

Interleaved winding and suppression of natural frequencies

Ideally, it is desirable to design and manufacture a transformer winding that can render all its internal resonances non-excitable. This study examines the effectiveness of an interleaved winding in achieving this goal. While investigating its effectiveness, it led to the establishment of a much desired theoretical basis that reinforces the reasons put forward in the literature to explain internal insulation failures observed in interleaved windings used in extra high voltage (EHV) transformers. Numerical calculations along with experimental verification on actual transformer windings are presented. This study reveals that most of the natural frequencies that are normally non-excitable in the line and neutral current responses of an interleaved winding have been rendered excitable in the disk-to-disk voltages, thus, providing favourable conditions for insulation overstress because of resonant overvoltages. Prevalence of such a condition is an inherent characteristic of interleaved windings.

An 8-to-1 bit 1-MS/s SAR ADC With VGA and Integrated Data Compression for Neural Recording

Low power consumption per channel and data rate minimization are two key challenges which need to be addressed in future generations of neural recording systems (NRS). Power consumption can be reduced by avoiding unnecessary processing whereas data rate is greatly decreased by sending spike time-stamps along with spike features as opposed to raw digitized data. Dynamic range in NRS can vary with time due to change in electrode-neuron distance or background noise, which demands adaptability. An analog-to-digital converter (ADC) is one of the most important blocks in a NRS. This paper presents an 8-bit SAR ADC in 0.13-mu m CMOS technology along with input and reference buffer. A novel energy efficient digital-to-analog converter switching scheme is proposed, which consumes 37% less energy than the present state-of-the-art. The use of a ping-pong input sampling scheme is emphasized for multichannel input to alleviate the bandwidth requirement of the input buffer. To reduce the data rate, the A/D process is only enabled through the in-built background noise rejection logic to ensure that the noise is not processed. The ADC resolution can be adjusted from 8 to 1 bit in 1-bit step based on the input dynamic range. The ADC consumes 8.8 mu W from 1 V supply at 1 MS/s speed. It achieves effective number of bits of 7.7 bits and FoM of 42.3 fJ/conversion-step.