994 resultados para voltage improvement


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Investigations on the electrical switching, structural, optical and photoacoustic analysis have been undertaken on chalcogenide GeSe1.5S0.5 thin films of various thicknesses prepared by vacuum evaporation technique. The decrease of band gap energy with increase in film thickness has been explained using the `density of states model'. The structural units of the films are characterized using Raman spectroscopy and the deconvoluted Raman peaks obtained from Gaussian fit around 188 cm(-1), 204 cm(-1) and 214 cm(-1) favors Ge-chalcogen tetrahedral units forming corner and edge sharing tetrahedra. All the thin films samples have been exhibited memory-type electrical switching behavior. An enhancement in the threshold voltages of GeSe1.5S0.5 thin films have been observed with increase in film thickness. The thickness dependence of switching voltages provide an insight into the switching mechanism and it is explained by the Joule heating effect. (C) 2014 Elsevier B.V. All rights reserved.

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High-power voltage-source inverters (VSI) are often switched at low frequencies due to switching loss constraints. Numerous low-switching-frequency PWM techniques have been reported, which are quite successful in reducing the total harmonic distortion under open-loop conditions at such low operating frequencies. However, the line current still contains low-frequency components (though of reduced amplitudes), which are fed back to the current loop controller during closed-loop operation. Since the harmonic frequencies are quite low and are not much higher than the bandwidth of the current loop, these are amplified by the current controller, causing oscillations and instability. Hence, only the fundamental current should be fed back. Filtering out these harmonics from the measured current (before feeding back) leads to phase shift and attenuation of the fundamental component, while not eliminating the harmonics totally. This paper proposes a method for on-line extraction of the fundamental current in induction motor drives, modulated with low-switching-frequency PWM. The proposed method is validated through simulations on MATLAB/Simulink. Further, the proposed algorithm is implemented on Cyclone FPGA based controller board. Experimental results are presented for an R-L load.

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Dead-time is introduced between the gating signals to the top and bottom switches in a voltage source inverter (VSI) leg, to prevent shoot through fault due to the finite turn-off times of IGBTs. The dead-time results in a delay when the incoming device is an IGBT, resulting in error voltage pulses in the inverter output voltage. This paper presents the design, fabrication and testing of an advanced gate driver, which eliminates dead-time and consequent output distortion. Here, the gating pulses are generated such that the incoming IGBT transition is not delayed and shoot-through is also prevented. The various logic units of the driver card and fault tolerance of the driver are verified through extensive tests on different topologies such as chopper, half-bridge and full-bridge inverter, and also at different conditions of load. Experimental results demonstrate the improvement in the load current waveform quality with the proposed circuit, on account of elimination of dead-time.

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Temperature dependent current-voltage (I-V) measurements of electrochemically prepared zinc oxide nanowire/polypyrrole (ZnONW/PPy) nanocomposite yielded non-linear I-V characteristics at temperatures between 300 and 4.5 K. The low-field conductance (G) of the ZnONW/PPy film exhibits pronounced temperature dependence with room temperature conductance (G(300K)) similar to 10(-3) S and a conductance ratio (G(300)K/G(4.5K)) of similar to 10(4), indicating dominance of significant temperature dependent charge transport processes. The conduction mechanism of the film is satisfactorily understood by extended fluctuation induced tunneling (FIT) model as the non-linear I-V characteristics fit fairly well to the extended FIT model. Further, the temperature dependence of G(o) obtained from fitting followed Sheng's model also. (C) 2014 AIP Publishing LLC.

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Multilevel inverters with dodecagonal (12-sided polygon) voltage space vector structure have advantages, such as complete elimination of fifth and seventh harmonics, reduction in electromagnetic interference, reduction in device voltage ratings, reduction of switching frequency, extension of linear modulation range, etc., making it a viable option for high-power medium-voltage drives. This paper proposes two power circuit topologies capable of generating multilevel dodecagonal voltage space vector structure with symmetric triangles (for the first time) with minimum number of dc-link power supplies and floating capacitor H-bridges. The first power topology is composed of two hybrid cascaded five-level inverters connected to either side of an open-end winding induction machine. Each inverter consists of a three-level neutral-point-clamped inverter, which is cascaded with an isolated H-bridge making it a five-level inverter. The second topology is for a normal induction motor. Both of these circuit topologies have inherent capacitor balancing for floating H-bridges for all modulation indexes, including transient operations. The proposed topologies do not require any precharging circuitry for startup. A simple pulsewidth modulation timing calculation method for space vector modulation is also presented in this paper. Due to the symmetric arrangement of congruent triangles within the voltage space vector structure, the timing computation requires only the sampled reference values and does not require any offline computation, lookup tables, or angle computation. Experimental results for steady-state operation and transient operation are also presented to validate the proposed concept.

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Optimal switching angles for minimization of total harmonic distortion of line current (I-THD) in a voltage source inverter are determined traditionally by imposing half-wave symmetry (HWS) and quarter-wave symmetry (QWS) conditions on the pulse width modulated waveform. This paper investigates optimal switching angles with QWS relaxed. Relaxing QWS expands the solution space and presents the possibility of improved solutions. The optimal solutions without QWS are shown here to outperform the optimal solutions with QWS over a range of modulation index (M) between 0.82 and 0.94 for a switching frequency to fundamental frequency ratio of 5. Theoretical and experimental results are presented on a 2.3kW induction motor drive.

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Enhancement of superconducting transition temperature (T-c) of parent superconductor, Fe1+xSe, of `Fe-11' family by Cr-substitution for excess Fe has been motivated us to investigate the effect of Cr-substitution in optimal superconductor or Fe1+xSe0.5Te0.5 at Fe site. Here, we report structural, magnetic, electrical transport, thermal transport and heat capacity properties or Cr-substitute compounds. x-ray diffraction measurement confirms the substitution of Cr-atoms in host lattice. Magnetic and electrical transport measurements are used to explore the superconducting properties where Cr-substituted compounds show improvement in superconducting diamagnetic fraction with same T-c as undoped one Heat capacity measurement confirms the bulk superconducting properties of compounds. Thermopower measurement characterizes the type of charge carriers in normal state. (C) 2015 Elsevier Ltd. All rights reserved.

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This paper presents a low energy memory decoder architecture for ultra-low-voltage systems containing multiple voltage domains. Due to limitations in scalability of memory supply voltages, these systems typically contain a core operating at subthreshold voltages and memories operating at a higher voltage. This difference in voltage provides a timing slack on the memory path as the core supply is scaled. The paper analyzes the feasibility and trade-offs in utilizing this timing slack to operate a greater section of memory decoder circuitry at the lower supply. A 256x16-bit SRAM interface has been designed in UMC 65nm low-leakage process to evaluate the above technique with the core and memory operating at 280 mV and 500 mV respectively. The technique provides a reduction of up to 20% in energy/cycle of the row decoder without any penalty in area and system-delay.

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A neonatal temperature monitoring system operating in subthreshold regime that utilizes time mode signal processing is presented. Resistance deviations in a thermistor due to temperature variations are converted to delay variations that are subsequently quantized by a Delay measurement unit (DMU). The DMU does away with the need for any analog circuitry and is synthesizable entirely from digital logic. An FPGA implementation of the system demonstrates the viability of employing time mode signal processing, and measured results show that temperature resolution better than 0.1 degrees C can be achieved using this approach.

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Cell voltage for a fully charged-substrate-integrated lead-carbon hybrid ultracapacitor is about 2.3 V. Therefore, for applications requiring higher DC voltage, several of these ultracapacitors need to be connected in series. However, voltage distribution across each series-connected ultracapacitor tends to be uneven due to tolerance in capacitance and parasitic parallel-resistance values. Accordingly, voltage-management circuit is required to protect constituent ultracapacitors from exceeding their rated voltage. In this study, the design and characterization of the substrate-integrated lead-carbon hybrid ultracapacitor with co-located terminals is discussed. Voltage-management circuit for the ultracapacitor is presented, and its effectiveness is validated experimentally.

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Rechargeable batteries based on Li and Na ions have been growing leaps and bounds since their inception in the 1970s. They enjoy significant attention from both the fundamental science point of view and practical applications ranging from portable electronics to hybrid vehicles and grid storage. The steady demand for building better batteries calls for discovery, optimisation and implementation of novel positive insertion (cathode) materials. In this quest, chemists have tried to unravel many future cathode materials by taking into consideration their eco-friendly synthesis, material/process economy, high energy density, safety, easy handling and sustainability. Interestingly, sulfate-based cathodes offer a good combination of sustainable syntheses and high energy density owing to their high-voltage operation, stemming from electronegative SO42- units. This review delivers a sneak peak at the recent advances in the discovery and development of sulfate-containing cathode materials by focusing on their synthesis, crystal structure and electrochemical performance. Several family of cathodes are independently discussed. They are 1) fluorosulfates AMSO(4)F], 2) bihydrated fluorosulfates AMSO(4)F2H(2)O], 3) hydroxysulfate AMSO(4)OH], 4) bisulfates A(2)M(SO4)(2)], 5) hydrated bisulfates A(2)M(SO4)(2)nH(2)O], 6) oxysulfates Fe-2(SO4)(2)O] and 7) polysulfates A(2)M(2)(SO4)(3)]. A comparative study of these sulfate-based cathodes has been provided to offer an outlook on the future development of high-voltage polyanionic cathode materials for next-generation batteries.

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In this paper, a multilevel dodecagonal voltage space vector structure with nineteen concentric dodecagons is proposed for the first time. This space vector structure is achieved by cascading two sets of asymmetric three-level inverters with isolated H-bridges on either side of an open-end winding induction motor. The dodecagonal structure is made possible by proper selection of dc link voltages and switching states of the inverters. The proposed scheme retains all the advantages of multilevel topologies as well as the advantages of dodecagonal voltage space vector structure. In addition to that, a generic and simple method for calculation of pulsewidth modulation timings using only sampled reference values (v(alpha) and v(beta)) is proposed. This enables the scheme to be used for any closed-loop application such as vector control. In addition, a new method of switching technique is proposed, which ensures minimum switching while eliminating the fifth-and seventh-order harmonics and suppressing the eleventh and thirteenth harmonics, eliminating the need for bulky filters. The motor phase voltage is a 24-stepped wave-form for the entire modulation range thereby reducing the number of switchings of the individual inverter modules. Experimental results for steady-state operation, transient operation, including start-up have been presented and the results of fast Fourier transform analysis is also presented for validating the proposed concept.

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In this study, a new reactive power loss index (RPLI) is proposed for identification of weak buses in the system. This index is further used for determining the optimal locations for placement of reactive compensation devices in the power system for additional voltage support. The new index is computed from the reactive power support and loss allocation algorithm using Y-bus method for the system under intact condition and as well as critical/severe network contingencies cases. Fuzzy logic approach is used to select the important and critical/severe line contingencies from the contingency list. The inherent characteristics of the reactive power in system operation is properly addressed while determining the reactive power loss allocation to load buses. The proposed index is tested on sample 10-bus equivalent system and 72-bus practical equivalent system of Indian southern region power grid. The validation of the weak buses identification from the proposed index with that from other existing methods in the literature is carried out to demonstrate the effectiveness of the proposed index. Simulation results show that the identification of weak buses in the system from the new RPLI is completely non-iterative, thus requires minimal computational efforts as compared with other existing methods in the literature.

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An attempt has been made to bring out the influence on strength and volume change behavior of fabric changes and new cementitious compound formation in a soil upon addition of various lime contents and with curing periods. The effects of changes in fabric of treatment with various lime contents (0, 2,4 and 6%) and with curing periods (0, 7, 14 and 28 days) have been evaluated by one-dimensional consolidation tests, in terms of void ratio changes and compressibility. The strength of soil treated with different lime contents with curing periods up to 28 days, and with the optimum lime content of 6% up to one year has been determined by unconfined compression tests. Comparison of effects of lime on the strength and volume change behavior of the soil brings out that the formation of flocculated fabric and cation exchange significantly reduces the compressibility of soil but marginally increases the strength. Cementation of soil particles and filling with cementitious compounds of the voids of flocculated fabric in the soil marginally reduces the compressibility but significantly increases the strength. Thus, the mechanism of volume change behavior of soil treated with lower lime content at short curing periods is distinctly different from that of the soil treated with optimum lime content at longer curing periods. This is consistent with the increase in the permeability caused by the addition from 2 to 4% lime and the decrease following the addition of 6% lime. Changes consistent with mechanical behavior have been determined by scanning electron microscope, X-ray diffraction and thermal analyses, energy dispersive X-ray spectrometer and pH value in microstructure, mineralogy, chemical composition and alkalinity, respectively. (C) 2015 Published by Elsevier B.V.

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Clock synchronization in a wireless sensor network (WSN) is quite essential as it provides a consistent and a coherent time frame for all the nodes across the network. Typically, clock synchronization is achieved by message passing using a contention-based scheme for media access, like carrier sense multiple access (CSMA). The nodes try to synchronize with each other, by sending synchronization request messages. If many nodes try to send messages simultaneously, contention-based schemes cannot efficiently avoid collisions. In such a situation, there are chances of collisions, and hence, message losses, which, in turn, affects the convergence of the synchronization algorithms. However, the number of collisions can be reduced with a frame based approach like time division multiple access (TDMA) for message passing. In this paper, we propose a design to utilize TDMA-based media access and control (MAC) protocol for the performance improvement of clock synchronization protocols. The basic idea is to use TDMA-based transmissions when the degree of synchronization improves among the sensor nodes during the execution of the clock synchronization algorithm. The design significantly reduces the collisions among the synchronization protocol messages. We have simulated the proposed protocol in Castalia network simulator. The simulation results show that the proposed protocol significantly reduces the time required for synchronization and also improves the accuracy of the synchronization algorithm.