Cojoined Irregular Topology and Routing Table Generation for Network-on-Chip

Scalable Networks on Chips (NoCs) are needed to match the ever-increasing communication demands of large-scale Multi-Processor Systems-on-chip (MPSoCs) for multi media communication applications. The heterogeneous nature of application specific on-chip cores along with the specific communication requirements among the cores calls for the design of application-specific NoCs for improved performance in terms of communication energy, latency, and throughput. In this work, we propose a methodology for the design of customized irregular networks-on-chip. The proposed method exploits a priori knowledge of the applications communication characteristic to generate an optimized network topology and corresponding routing tables.

A Shapley Value Analysis to Coordinate the Formation of Procurement Networks

In this paper we address the problem of forming procurement networks for items with value adding stages that are linearly arranged. Formation of such procurement networks involves a bottom-up assembly of complex production, assembly, and exchange relationships through supplier selection and contracting decisions. Research in supply chain management has emphasized that such decisions need to take into account the fact that suppliers and buyers are intelligent and rational agents who act strategically. In this paper, we view the problem of procurement network formation (PNF) for multiple units of a single item as a cooperative game where agents cooperate to form a surplus maximizing procurement network and then share the surplus in a fair manner. We study the implications of using the Shapley value as a solution concept for forming such procurement networks. We also present a protocol, based on the extensive form game realization of the Shapley value, for forming these networks.

MODLEX: A Multi Objective Data Layout EXploration Framework for Embedded Systems-on-Chip

The memory subsystem is a major contributor to the performance, power, and area of complex SoCs used in feature rich multimedia products. Hence, memory architecture of the embedded DSP is complex and usually custom designed with multiple banks of single-ported or dual ported on-chip scratch pad memory and multiple banks of off-chip memory. Building software for such large complex memories with many of the software components as individually optimized software IPs is a big challenge. In order to obtain good performance and a reduction in memory stalls, the data buffers of the application need to be placed carefully in different types of memory. In this paper we present a unified framework (MODLEX) that combines different data layout optimizations to address the complex DSP memory architectures. Our method models the data layout problem as multi-objective genetic algorithm (GA) with performance and power being the objectives and presents a set of solution points which is attractive from a platform design viewpoint. While most of the work in the literature assumes that performance and power are non-conflicting objectives, our work demonstrates that there is significant trade-off (up to 70%) that is possible between power and performance.

MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip

Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and lower energy consumption. The memory architecture of the embedded system strongly influences these parameters. Hence the embedded system designer performs a complete memory architecture exploration. This problem is a multi-objective optimization problem and can be tackled as a two-level optimization problem. The outer level explores various memory architecture while the inner level explores placement of data sections (data layout problem) to minimize memory stalls. Further, the designer would be interested in multiple optimal design points to address various market segments. However, tight time-to-market constraints enforces short design cycle time. In this paper we address the multi-level multi-objective memory architecture exploration problem through a combination of Multi-objective Genetic Algorithm (Memory Architecture exploration) and an efficient heuristic data placement algorithm. At the outer level the memory architecture exploration is done by picking memory modules directly from a ASIC memory Library. This helps in performing the memory architecture exploration in a integrated framework, where the memory allocation, memory exploration and data layout works in a tightly coupled way to yield optimal design points with respect to area, power and performance. We experimented our approach for 3 embedded applications and our approach explores several thousand memory architecture for each application, yielding a few hundred optimal design points in a few hours of computation time on a standard desktop.

Surface effects on stacking fault and twin formation in fcc nanofilms: A first-principles study

The free surface effects on stacking fault and twin formation in fcc metals (Al, Cu, and Ni) were examined by first-principles calculations based on density functional theory (DFT). It is found that the generalized planar fault (GPF) energies of Ni are much larger than bulk Ni with respect to Al and Cu. The discrepancy is attributed to the localized relaxation of Ni nanofilm to accommodate the large expansion of the inter-planar separation induced at the fault plane. The localized relaxation can be coupled to the electronic structure of Ni nanofilms. (C) 2011 Elsevier B.V. All rights reserved.

The role of surface texture on friction and transfer layer formation during repeated sliding of Al-4Mg against steel

In the present investigation, various kinds of textures, namely, unidirectional, 8-ground, and random were attained on the die surfaces. Roughness of the textures was varied using different grits of emery papers or polishing powders. Then pins made of Al-4Mg alloys were slid against steel plates at various numbers of cycles, namely, 1, 3, 5, 10 and 20 using pin-on-plate reciprocating sliding tester. Tests were conducted at a sliding velocity of 2 minis in ambient conditions under both dry and lubricated conditions. A constant normal load of 35 N was applied in the tests. The morphologies of the worn surfaces of the pins and the formation of transfer layer on the counter surfaces were observed using a scanning electron microscope. Surface roughness parameters of the plates were measured using an optical profilometer. In the experiments, it was observed that the coefficient of friction and formation of the transfer layer depend on the die surface textures under both dry and lubricated conditions. More specifically, the coefficient of friction decreases for unidirectional and 8-ground surfaces while for random surfaces it increases with number of cycles. However, the coefficient of friction is highest for the sliding perpendicular to the unidirectional textures and least for the random textures under both dry and lubricated conditions. The difference in friction values between these two surfaces decreases with increasing number of cycles. The variation in the coefficient of friction under both dry and lubrication conditions is attributed to the change in texture of the surfaces during sliding. (C) 2011 Elsevier B.V. All rights reserved.