Multi Processor Systems On Chip with Configurable Hardware Acceleration

The evolution of the electronics embedded applications forces electronics systems designers to match their ever increasing requirements. This evolution pushes the computational power of digital signal processing systems, as well as the energy required to accomplish the computations, due to the increasing mobility of such applications. Current approaches used to match these requirements relies on the adoption of application specific signal processors. Such kind of devices exploits powerful accelerators, which are able to match both performance and energy requirements. On the other hand, the too high specificity of such accelerators often results in a lack of flexibility which affects non-recurrent engineering costs, time to market, and market volumes too. The state of the art mainly proposes two solutions to overcome these issues with the ambition of delivering reasonable performance and energy efficiency: reconfigurable computing and multi-processors computing. All of these solutions benefits from the post-fabrication programmability, that definitively results in an increased flexibility. Nevertheless, the gap between these approaches and dedicated hardware is still too high for many application domains, especially when targeting the mobile world. In this scenario, flexible and energy efficient acceleration can be achieved by merging these two computational paradigms, in order to address all the above introduced constraints. This thesis focuses on the exploration of the design and application spectrum of reconfigurable computing, exploited as application specific accelerators for multi-processors systems on chip. More specifically, it introduces a reconfigurable digital signal processor featuring a heterogeneous set of reconfigurable engines, and a homogeneous multi-core system, exploiting three different flavours of reconfigurable and mask-programmable technologies as implementation platform for applications specific accelerators. In this work, the various trade-offs concerning the utilization multi-core platforms and the different configuration technologies are explored, characterizing the design space of the proposed approach in terms of programmability, performance, energy efficiency and manufacturing costs.

Hardware/Software Design of Dynamic Real-Time Schedulers for Embedded Multiprocessor Systems

The new generation of multicore processors opens new perspectives for the design of embedded systems. Multiprocessing, however, poses new challenges to the scheduling of real-time applications, in which the ever-increasing computational demands are constantly flanked by the need of meeting critical time constraints. Many research works have contributed to this field introducing new advanced scheduling algorithms. However, despite many of these works have solidly demonstrated their effectiveness, the actual support for multiprocessor real-time scheduling offered by current operating systems is still very limited. This dissertation deals with implementative aspects of real-time schedulers in modern embedded multiprocessor systems. The first contribution is represented by an open-source scheduling framework, which is capable of realizing complex multiprocessor scheduling policies, such as G-EDF, on conventional operating systems exploiting only their native scheduler from user-space. A set of experimental evaluations compare the proposed solution to other research projects that pursue the same goals by means of kernel modifications, highlighting comparable scheduling performances. The principles that underpin the operation of the framework, originally designed for symmetric multiprocessors, have been further extended first to asymmetric ones, which are subjected to major restrictions such as the lack of support for task migrations, and later to re-programmable hardware architectures (FPGAs). In the latter case, this work introduces a scheduling accelerator, which offloads most of the scheduling operations to the hardware and exhibits extremely low scheduling jitter. The realization of a portable scheduling framework presented many interesting software challenges. One of these has been represented by timekeeping. In this regard, a further contribution is represented by a novel data structure, called addressable binary heap (ABH). Such ABH, which is conceptually a pointer-based implementation of a binary heap, shows very interesting average and worst-case performances when addressing the problem of tick-less timekeeping of high-resolution timers.

Advances in hardware and molecular design of polarizing agents for dynamic nuclear polarization

Die Kernmagnetresonanz (NMR) ist eine vielseitige Technik, die auf spin-tragende Kerne angewiesen ist. Seit ihrer Entdeckung ist die Kernmagnetresonanz zu einem unverzichtbaren Werkzeug in unzähligen Anwendungen der Physik, Chemie, Biologie und Medizin geworden. Das größte Problem der NMR ist ihre geringe Sensitivtät auf Grund der sehr kleinen Energieaufspaltung bei Raumtemperatur. Für Protonenspins, die das größte magnetogyrische Verhältnis besitzen, ist der Polarisationsgrad selbst in den größten verfügbaren Magnetfeldern (24 T) nur ~7*10^(-5).rnDurch die geringe inhärente Polarisation ist folglich eine theoretische Sensitivitätssteigerung von mehr als 10^4 möglich. rnIn dieser Arbeit wurden verschiedene technische Aspekte und unterschiedliche Polarisationsagenzien für Dynamic Nuclear Polarization (DNP) untersucht.rnDie technische Entwicklung des mobilen Aufbaus umfasst die Verwendung eines neuen Halbach Magneten, die Konstruktion neuer Probenköpfe und den automatisierten Ablauf der Experimente mittels eines LabVIEW basierten Programms. Desweiteren wurden zwei neue Polarisationsagenzien mit besonderen Merkmalen für den Overhauser und den Tieftemperatur DNP getestet. Zusätzlich konnte die Durchführbarkeit von NMR Experimenten an Heterokernen (19F und 13C) im mobilen Aufbau bei 0,35 T gezeigt werden. Diese Ergebnisse zeigen die Möglichkeiten der Polarisationstechnik DNP auf, wenn Heterokerne mit einem kleinen magnetogyrischen Verhältnis polarisiert werden müssen.rnDie Sensitivitätssteigerung sollte viele neue Anwendungen, speziell in der Medizin, ermöglichen.

Test hardware del primo batch di schede rod per l'esperimento atlas ibl.

L’acceleratore di particelle LHC, al CERN di Ginevra, permette studi molto rilevanti nell'ambito della fisica subnucleare. L’importanza che ricopre in questo campo il rivelatore è grandissima ed è per questo che si utilizzano tecnologie d’avanguardia nella sua costruzione. É altresì fondamentale disporre di un sistema di acquisizione dati quanto più moderno ma sopratutto efficiente. Tale sistema infatti è necessario per gestire tutti i segnali elettrici che derivano dalla conversione dell’evento fisico, passaggio necessario per rendere misurabili e quantificabili le grandezze di interesse. In particolare in questa tesi viene seguito il lavoro di test delle schede ROD dell’esperimento ATLAS IBL, che mira a verificare la loro corretta funzionalità, prima che vengano spedite nei laboratori del CERN. Queste nuove schede gestiscono i segnali in arrivo dal Pixel Detector di ATLAS, per poi inviarli ai computer per la successiva elaborazione. Un sistema simile era già implementato e funzionante, ma il degrado dei chip ha causato una perdita di prestazioni, che ha reso necessario l’inserimento di un layer aggiuntivo. Il nuovo strato di rivelatori a pixel, denominato Insertable Barrel Layer (IBL), porta così un aggiornamento tecnologico e prestazionale all'interno del Pixel Detector di ATLAS, andando a ristabilire l’efficacia del sistema.

Many-Core Architectures: Hardware-Software Optimization and Modeling Techniques

During the last few decades an unprecedented technological growth has been at the center of the embedded systems design paramount, with Moore’s Law being the leading factor of this trend. Today in fact an ever increasing number of cores can be integrated on the same die, marking the transition from state-of-the-art multi-core chips to the new many-core design paradigm. Despite the extraordinarily high computing power, the complexity of many-core chips opens the door to several challenges. As a result of the increased silicon density of modern Systems-on-a-Chip (SoC), the design space exploration needed to find the best design has exploded and hardware designers are in fact facing the problem of a huge design space. Virtual Platforms have always been used to enable hardware-software co-design, but today they are facing with the huge complexity of both hardware and software systems. In this thesis two different research works on Virtual Platforms are presented: the first one is intended for the hardware developer, to easily allow complex cycle accurate simulations of many-core SoCs. The second work exploits the parallel computing power of off-the-shelf General Purpose Graphics Processing Units (GPGPUs), with the goal of an increased simulation speed. The term Virtualization can be used in the context of many-core systems not only to refer to the aforementioned hardware emulation tools (Virtual Platforms), but also for two other main purposes: 1) to help the programmer to achieve the maximum possible performance of an application, by hiding the complexity of the underlying hardware. 2) to efficiently exploit the high parallel hardware of many-core chips in environments with multiple active Virtual Machines. This thesis is focused on virtualization techniques with the goal to mitigate, and overtake when possible, some of the challenges introduced by the many-core design paradigm.

OpenMP task scheduling strategies to mitigate hardware variability in tightly-coupled shared memory clusters

In questa tesi sono stati apportati due importanti contributi nel campo degli acceleratori embedded many-core. Abbiamo implementato un runtime OpenMP ottimizzato per la gestione del tasking model per sistemi a processori strettamente accoppiati in cluster e poi interconnessi attraverso una network on chip. Ci siamo focalizzati sulla loro scalabilità e sul supporto di task di granularità fine, come è tipico nelle applicazioni embedded. Il secondo contributo di questa tesi è stata proporre una estensione del runtime di OpenMP che cerca di prevedere la manifestazione di errori dati da fenomeni di variability tramite una schedulazione efficiente del carico di lavoro.

Test hardware del secondo batch di schede ROD per il layer 2 del pixel detector dell'esperimento ATLAS al CERN

In questa tesi viene seguito il lavoro di test delle schede ROD del layer 2 del Pixel Detector dell’ esperimento ATLAS, che mira a verificare la loro corretta funzionalità, prima che vengano spedite nei laboratori del CERN. Queste nuove schede gestiscono i segnali in arrivo dal Pixel Detector di ATLAS, per poi inviarli ai computer per la successiva elaborazione. Le schede ROD andranno a sostituire le precedenti schede SiROD nella catena di acquisizione dati dell’esperimento, procedendo dal nuovo strato IBL, e proseguendo con i tre layer del Pixel Detector, corroborando l’aggiornamento tecnologico e prestazionale necessario in vista dell’incremento di luminosità dell’esperimento.

Realizzazione di un sistema di automazione domotica con tecnologia open-hardware

Il termine Domotica deriva dall’unione dei termini domus e robotics e spazia oltre alle competenze in ambito informatico ed elettronico, avvalendosi dell’architettura e di determinati campi dell’ingegneria come: energetica, edile, dell’ automazione, elettrotecnica, delle telecomunicazioni. La Domotica agevola gli aspetti della quotidianità all’interno dell’ambiente casalingo o, più in generale, di ambienti antropizzati. Questa tesi ha l’intento di spiegare come può essere realizzato un sistema domotizzato casalingo utilizzando dispositivi open-hardware. Inizialmente verranno messi in chiaro i concetti chiave generici di un sistema domotico e verranno discussi i prodotti attualmente in commercio e verrà fatta una piccola introduzione sul concetto di open-hardware. Successivamente verrà discusso il sistema realizzato dandone una panoramica, si esaminerà la strutturazione sia software che hardware e le tecnologie ed i dispositivi utilizzati, per poi enucleare casi d’uso. A seguire le conclusioni.

Hardware accelerated ray cast of volume data and volume gradient for an optimized splines-based multi-resolution 2D-3D registration

This paper describes a method for DRR generation as well as for volume gradients projection using hardware accelerated 2D texture mapping and accumulation buffering and demonstrates its application in 2D-3D registration of X-ray fluoroscopy to CT images. The robustness of the present registration scheme are guaranteed by taking advantage of a coarse-to-fine processing of the volume/image pyramids based on cubic B-splines. A human cadaveric spine specimen together with its ground truth was used to compare the present scheme with a purely software-based scheme in three aspects: accuracy, speed, and capture ranges. Our experiments revealed an equivalent accuracy and capture ranges but with much shorter registration time with the present scheme. More specifically, the results showed 0.8 mm average target registration error, 55 second average execution time per registration, and 10 mm and 10° capture ranges for the present scheme when tested on a 3.0 GHz Pentium 4 computer.