You Should Never Look a Gift Horse in the Mouth: One-Size-Fits-All Compensation in Wrongful Conception

This article reconsiders the House of Lords decision in Rees v. Darlington Memorial Hospital NHS Trust (2003) and the decision to award a conventional award of £15,000 in all cases of failed sterilisation resulting in the birth of an unwanted child. In so doing, it briefly recites the history of the Wrongful Conception action and the unique facts of Rees. It then goes on the consider the implications of two fundamental aspects of the judgment. Firstly, it looks at the 'conventional award' itself and considers the reasoning behind the award and the effect that it has on our understanding of (particularly women's) reproductive autonomy. Secondly, it analyses the rather 'unique' judgment of Lord Scott and his decision to evaluate these cases using the possessory analogy of an unwanted foal; particular focus is given to the notion of parental 'choice' in these cases and whether mitigation (i.e. abortion or adoption) can ever be considered "reasonable".

Reference clock design for low power and low phase noise with temperature compensation

Thesis (Ph.D.)--University of Washington, 2016-03

Reactive power compensation by EPSO technique

This paper presents a methodology to address reactive power compensation using Evolutionary Particle Swarm Optimization (EPSO) technique programmed in the MATLAB environment. The main objective is to find the best operation point minimizing power losses with reactive power compensation, subjected to all operational constraints, namely full AC power flow equations, active and reactive power generation constraints. The methodology has been tested with the IEEE 14 bus test system demonstrating the ability and effectiveness of the proposed approach to handle the reactive power compensation problem.

Optimal dispatch with reactive power compensation by Genetic Algorithm

This paper presents a Unit Commitment model with reactive power compensation that has been solved by Genetic Algorithm (GA) optimization techniques. The GA has been developed a computational tools programmed/coded in MATLAB. The main objective is to find the best generations scheduling whose active power losses are minimal and the reactive power to be compensated, subjected to the power system technical constraints. Those are: full AC power flow equations, active and reactive power generation constraints. All constraints that have been represented in the objective function are weighted with a penalty factors. The IEEE 14-bus system has been used as test case to demonstrate the effectiveness of the proposed algorithm. Results and conclusions are dully drawn.

Proposta de um algoritmo eficiente para a localização de faltas por relé diferencial numérico para proteção de linhas de transmissão com compensação série controlada por tiristores (TCSC)

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

Multi-μ: an Ada 95 based architecture for fault tolerance support of real-time systems

This paper presents an architecture (Multi-μ) being implemented to study and develop software based fault tolerant mechanisms for Real-Time Systems, using the Ada language (Ada 95) and Commercial Off-The-Shelf (COTS) components. Several issues regarding fault tolerance are presented and mechanisms to achieve fault tolerance by software active replication in Ada 95 are discussed. The Multi-μ architecture, based on a specifically proposed Fault Tolerance Manager (FTManager), is then described. Finally, some considerations are made about the work being done and essential future developments.

A comparative analysis of fault injection methods via enhanced on-chip debug infrastructures

On-chip debug (OCD) features are frequently available in modern microprocessors. Their contribution to shorten the time-to-market justifies the industry investment in this area, where a number of competing or complementary proposals are available or under development, e.g. NEXUS, CJTAG, IJTAG. The controllability and observability features provided by OCD infrastructures provide a valuable toolbox that can be used well beyond the debugging arena, improving the return on investment rate by diluting its cost across a wider spectrum of application areas. This paper discusses the use of OCD features for validating fault tolerant architectures, and in particular the efficiency of various fault injection methods provided by enhanced OCD infrastructures. The reference data for our comparative study was captured on a workbench comprising the 32-bit Freescale MPC-565 microprocessor, an iSYSTEM IC3000 debugger (iTracePro version) and the Winidea 2005 debugging package. All enhanced OCD infrastructures were implemented in VHDL and the results were obtained by simulation within the same fault injection environment. The focus of this paper is on the comparative analysis of the experimental results obtained for various OCD configurations and debugging scenarios.

Real time fault injection using a modified debugging infrastructure

Dependability is a critical factor in computer systems, requiring high quality validation & verification procedures in the development stage. At the same time, digital devices are getting smaller and access to their internal signals and registers is increasingly complex, requiring innovative debugging methodologies. To address this issue, most recent microprocessors include an on-chip debug (OCD) infrastructure to facilitate common debugging operations. This paper proposes an enhanced OCD infrastructure with the objective of supporting the verification of fault-tolerant mechanisms through fault injection campaigns. This upgraded on-chip debug and fault injection (OCD-FI) infrastructure provides an efficient fault injection mechanism with improved capabilities and dynamic behavior. Preliminary results show that this solution provides flexibility in terms of fault triggering and allows high speed real-time fault injection in memory elements

Real time fault injection using enhanced OCD -- a performance analysis

Fault injection is frequently used for the verification and validation of dependable systems. When targeting real time microprocessor based systems the process becomes significantly more complex. This paper proposes two complementary solutions to improve real time fault injection campaign execution, both in terms of performance and capabilities. The methodology is based on the use of the on-chip debug mechanisms present in modern electronic devices. The main objective is the injection of faults in microprocessor memory elements with minimum delay and intrusiveness. Different configurations were implemented and compared in terms of performance gain and logic overhead.

Real-time fault injection using enhanced on-chip debug infrastructures

The rapid increase in the use of microprocessor-based systems in critical areas, where failures imply risks to human lives, to the environment or to expensive equipment, significantly increased the need for dependable systems, able to detect, tolerate and eventually correct faults. The verification and validation of such systems is frequently performed via fault injection, using various forms and techniques. However, as electronic devices get smaller and more complex, controllability and observability issues, and sometimes real time constraints, make it harder to apply most conventional fault injection techniques. This paper proposes a fault injection environment and a scalable methodology to assist the execution of real-time fault injection campaigns, providing enhanced performance and capabilities. Our proposed solutions are based on the use of common and customized on-chip debug (OCD) mechanisms, present in many modern electronic devices, with the main objective of enabling the insertion of faults in microprocessor memory elements with minimum delay and intrusiveness. Different configurations were implemented starting from basic Components Off-The-Shelf (COTS) microprocessors, equipped with real-time OCD infrastructures, to improved solutions based on modified interfaces, and dedicated OCD circuitry that enhance fault injection capabilities and performance. All methodologies and configurations were evaluated and compared concerning performance gain and silicon overhead.

A framework for fault tolerant real time systems based on reconfigurable FPGAs

To increase the amount of logic available to the users in SRAM-based FPGAs, manufacturers are using nanometric technologies to boost logic density and reduce costs, making its use more attractive. However, these technological improvements also make FPGAs particularly vulnerable to configuration memory bit-flips caused by power fluctuations, strong electromagnetic fields and radiation. This issue is particularly sensitive because of the increasing amount of configuration memory cells needed to define their functionality. A short survey of the most recent publications is presented to support the options assumed during the definition of a framework for implementing circuits immune to bit-flips induction mechanisms in memory cells, based on a customized redundant infrastructure and on a detection-and-fix controller.

A modified debugging infrastructure to assist real time fault injection campaigns

Fault injection is frequently used for the verification and validation of the fault tolerant features of microprocessors. This paper proposes the modification of a common on-chip debugging (OCD) infrastructure to add fault injection capabilities and improve performance. The proposed solution imposes a very low logic overhead and provides a flexible and efficient mechanism for the execution of fault injection campaigns, being applicable to different target system architectures.

A tutela preventiva da responsabilidade civil

The contemporary society is characterized by high risks. Today, the prevention of damages is as important as compensation. This is due to the fact that the potentiality of several damages is not in line with compensation, because often compensation proves to be impossible. Civil law should be at the service of the citizens, which explains that the heart of the institution of non-contractual liability has gradually moved towards the victim's protection. It is requested from Tort law an active attitude that seeks to avoid damages, reducing its dimension and frequency. The imputation by risk proves to be necessary and useful in the present context as it demonstrates the ability to model behaviors, functioning as a warning for agents engaged in hazardous activities. Economically, it seeks to prevent socially inefficient behaviors. Strict liability assumes notorious importance as a deterrent and in the dispersion of damage by society. The paradigm of the imputation founded on fault has proved insufficient for the effective protection of the interests of the citizens, particularly if based in an anachronistic vision of the concept of fault. Prevention arises in several areas, especially in environmental liability, producer liability and liability based on infringement of copyright and rights relating to the personality. To overcome the damage as the gauge for compensation does not inevitably mean the recognition of the punitive approach. Prevention should not be confused with reactive/punitive objectives. The deterrence of unlawful conduct is not subordinated to punishment.