916 resultados para DC voltage droop control
Resumo:
The voltage ripple and power loss in the DC-capacitor of a voltage source inverter depend on the harmonic currents flowing through the capacitor. This paper presents double Fourier series based harmonic analysis of DC capacitor current in a three-level neutral point clamped inverter, modulated with sine-triangle PWM. The analytical results are validated experimentally on a 5-kVA three-level inverter prototype. The results of the analysis are used for predicting the power loss in the DC capacitor.
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In the present paper, a novel topology for generating a 17-level inverter using three-level flying capacitor inverter and cascaded H-bridge modules with floating capacitors. The proposed circuit is analyzed and various aspects of it are presented in the paper. This circuit is experimentally verified and the results are shown. The stability of the capacitor balancing algorithm has been verified during sudden acceleration. This circuit has many pole voltage redundancies. This circuit has an advantage of balancing all the capacitor voltages instantaneously by switching through the redundancies. Another advantage of this topology is its ability to generate all the 17 pole voltages from a single DC link which enables back to back converter operation. Also, the proposed inverter can be operated at all load power factors and modulation indices. Another advantage is, if one of the H-bridges fail, the inverter can still be operated at full load with reduced number of levels.
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In this paper, a current error space vector (CESV) based hysteresis controller for a 12-sided polygonal voltage space vector inverter fed induction motor (IM) drive is proposed, for the first time. An open-end winding configuration is used for the induction motor. The proposed controller uses parabolic boundary with generalized vector selection logic for all sectors. The drive scheme is first studied with a space vector based PWM (SVPWM) control and from this the current error space phasor boundary is obtained. This current error space phasor boundary is approximated with four parabolas and then the system is run with space phasor based hysteresis PWM controller by limiting the CESV within the parabolic boundary. The proposed controller has increased modulation range, absence of 5th and 7th order harmonics for the entire modulation range, nearly constant switching frequency, fast dynamic response with smooth transition to the over modulation region and a simple controller implementation.
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We have investigated the effect of post- deposition annealing on the composition and electrical properties of alumina (Al2O3) thin films. Al2O3 were deposited on n-type Si < 100 >. substrates by dc reactive magnetron sputtering. The films were subjected to post- deposition annealing at 623, 823 and 1023 K in vacuum. X-ray photoelectron spectroscopy results revealed that the composition improved with post- deposition annealing, and the film annealed at 1023 K became stoichiometric with an O/Al atomic ratio of 1.49. Al/Al2O3/Si metal-oxide-semiconductor (MOS) structures were then fabricated, and a correlation between the dielectric constant epsilon(r) and interface charge density Q(i) with annealing conditions were studied. The dielectric constant of the Al2O3 thin films increased to 9.8 with post- deposition annealing matching the bulk value, whereas the oxide charge density decreased to 3.11 x 10(11) cm(-2.) Studies on current-voltage IV characteristics indicated ohmic and Schottky type of conduction at lower electric fields (<0.16 MV cm(-1)) and space charge limited conduction at higher electric fields.
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Multilevel inverters with dodecagonal (12-sided polygon) voltage space vector structure have advantages, such as complete elimination of fifth and seventh harmonics, reduction in electromagnetic interference, reduction in device voltage ratings, reduction of switching frequency, extension of linear modulation range, etc., making it a viable option for high-power medium-voltage drives. This paper proposes two power circuit topologies capable of generating multilevel dodecagonal voltage space vector structure with symmetric triangles (for the first time) with minimum number of dc-link power supplies and floating capacitor H-bridges. The first power topology is composed of two hybrid cascaded five-level inverters connected to either side of an open-end winding induction machine. Each inverter consists of a three-level neutral-point-clamped inverter, which is cascaded with an isolated H-bridge making it a five-level inverter. The second topology is for a normal induction motor. Both of these circuit topologies have inherent capacitor balancing for floating H-bridges for all modulation indexes, including transient operations. The proposed topologies do not require any precharging circuitry for startup. A simple pulsewidth modulation timing calculation method for space vector modulation is also presented in this paper. Due to the symmetric arrangement of congruent triangles within the voltage space vector structure, the timing computation requires only the sampled reference values and does not require any offline computation, lookup tables, or angle computation. Experimental results for steady-state operation and transient operation are also presented to validate the proposed concept.
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This paper presents the experimental results for an attractive control scheme implementation using an 8 bit microcontroller. The power converter involved is a 3 phase full controlled bridge rectifier. A single quadrant DC drive has been realized and results have been presented for both open and closed loop implementations.
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The charge-pump (CP) mismatch current is a dominant source of static phase error and reference spur in the nano-meter CMOS PLL implementations due to its worsened channel length modulation effect. This paper presents a charge-pump (CP) mismatch current reduction technique utilizing an adaptive body bias tuning of CP transistors and a zero CP mismatch current tracking PLL architecture for reference spur suppression. A chip prototype of the proposed circuit was implemented in 0.13 mu m CMOS technology. The frequency synthesizer consumes 8.2 mA current from a 13 V supply voltage and achieves a phase noise of -96.01 dBc/Hz @ 1 MHz offset from a 2.4 GHz RF carrier. The charge-pump measurements using the proposed calibration technique exhibited a mismatch current of less than 0.3 mu A (0.55%) over the VCO control voltage range of 0.3-1.0 V. The closed loop measurements show a minimized static phase error of within +/- 70 ps and a similar or equal to 9 dB reduction in reference spur level across the PLL output frequency range 2.4-2.5 GHz. The presented CP calibration technique compensates for the DC current mismatch and the mismatch due to channel length modulation effect and therefore improves the performance of CP-PLLs in nano-meter CMOS implementations. (C) 2015 Elsevier Ltd. All rights reserved.
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In the present work, electrospraying of an organic molecule is carried out using various solvents, obtaining fibril structures along with a range of distinct morphologies. Solvent characteristics play a major role in determining the morphology of the organic material. A thiophene derivative (7,9-di(thiophen-2-yl)-8H-cyclopentaa]acenaphthylen-8-one) (DTCPA) of donor-acceptor-donor (DAD) architecture is used to study this solvent effect. Seven solvents with decreasing vapour pressure are selected for experiments. Electrospraying is conducted at a solution concentration of 1.5 wt% and a constant applied voltage of 15 kV. Gradual transformation in morphology of the electrospun product from spiked-spheres to only spikes is observed. A mechanism describing this transformation is proposed based on electron micrograph analysis and XRD analysis. These data indicate that the morphological change is due to the synergistic effect of both vapour pressure and dielectric constant of the solvents. Through a reasonable control of the crystallite size and morphology along with the proposal of the transformation mechanism, this study elucidates electrospraying as a prospective method for designing architectures in organic electronics.
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This paper proposes a novel decision making framework for optimal transmission switching satisfying the AC feasibility, stability and circuit breaker (CB) reliability requirements needed for practical implementation. The proposed framework can be employed as a corrective tool in day to day operation planning scenarios in response to potential contingencies. The switching options are determined using an efficient heuristic algorithm based on DC optimal power flow, and are presented in a multi-branch tree structure. Then, the AC feasibility and stability checks are conducted and the CB condition monitoring data are employed to perform a CB reliability and line availability assessment. Ultimately, the operator will be offered multiple AC feasible and stable switching options with associated benefits. The operator can use this information, other operating conditions not explicitly considered in the optimization, and his/her own experience to implement the best and most reliable switching action(s). The effectiveness of the proposed approach is validated on the IEEE-118 bus test system. (C) 2015 Elsevier B.V. All rights reserved.
Resumo:
With increasing energy demand, it necessitates to generate and transmit the electrical power with minimal losses. High voltage power transmission is the most economical way of transmitting bulk power over long distances. Transmission insulator is one of the main components used as a mechanical support and to electrically isolate the conductor from the tower. Corona from the hardware and conductors can significantly affect the performance of the polymeric insulators. In the present investigation a methodology is presented to evaluate the corona performance of the polymeric shed material under different environment conditions for both ac and dc excitation. The results of the comprehensive analysis on various polymeric samples and the power released from the corona electrode for both the ac and dc excitation are presented. Some interesting results obtained from the chemical analysis confirmed the presence of nitric acid species on the treated sample which in long term will affect the strength of the insulator, also the morphological changes were found to be varying for different experimental conditions. (C) 2015 The Authors. Published by Elsevier Ltd.
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In this paper, for the first time, the key design parameters of a shallow trench isolation-based drain-extended MOS transistor are discussed for RF power applications in advanced CMOS technologies. The tradeoff between various dc and RF figures of merit (FoMs) is carefully studied using well-calibrated TCAD simulations. This detailed physical insight is used to optimize the dc and RF behavior, and our work also provides a design window for the improvement of dc as well as RF FoMs, without affecting the breakdown voltage. An improvement of 50% in R-ON and 45% in RF gain is achieved at 1 GHz. Large-signal time-domain analysis is done to explore the output power capability of the device.
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Closed loop control of a grid connected VSI requires line current control and dc bus voltage control. The closed loop system comprising PR current controller and grid connected VSI with LCL filter is a higher order system. Closed loop control gain expressions are therefore difficult to obtain directly for such systems. In this work a simplified approach has been adopted to find current and voltage controller gain expressions for a 3 phase 4 wire grid connected VSI with LCL filter. The closed loop system considered here utilises PR current controller in natural reference frame and PI controller for dc bus voltage control. Asymptotic frequency response plot and gain bandwidth requirements of the system have been used for current control and voltage controller design. A simplified lower order model, derived for closed loop current control, is used for the dc bus voltage controller design. The adopted design method has been verified through experiments by comparison of the time domain response.
Resumo:
The voltage ripple and power loss in the DC-capacitor of a voltage source inverter depend on the harmonic currents flowing through the capacitor. This paper presents a double Fourier series based analysis of the harmonic contents of the DC capacitor current in a three-level neutral-point clamped (NPC) inverter, modulated with sine-triangle pulse-width modulation (SPWM) or conventional space vector pulse-width modulation (CSVPWM) schemes. The analytical results are validated experimentally on a 3-kVA three-level inverter prototype. The capacitor current in an NPC inverter has a periodicity of 120(a similar to) at the fundamental or modulation frequency. Hence, this current contains third-harmonic and triplen-frequency components, apart from switching frequency components. The harmonic components vary with modulation index and power factor for both PWM schemes. The third harmonic current decreases with increase in modulation index and also decreases with increase in power factor in case of both PWM methods. In general, the third harmonic content is higher with SPWM than with CSVPWM at a given operating condition. Also, power loss and voltage ripple in the DC capacitor are estimated for both the schemes using the current harmonic spectrum and equivalent series resistance (ESR) of the capacitor.
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A split-phase induction motor is fed from two three-phase voltage source inverters for speed control. This study analyses carrier-comparison based pulse width modulation (PWM) schemes for a split-phase motor drive, from a space-vector perspective. Sine-triangle PWM, one zero-sequence injection PWM where the same zero-sequence signal is used for both the inverters, and another zero-sequence injection PWM where different zero-sequence signals are employed for the two inverters are considered. The set of voltage vectors applied, the sequence in which the voltage vectors are applied, and the resulting current ripple vector are analysed for all the PWM methods. Besides all the PWM methods are compared in terms of dc bus utilisation. For the same three-phase sine reference, the PWM method with different zero-sequence signals for the two inverters is found to employ a set of vectors different from the other methods. Both analysis and experimental results show that this method results in lower total harmonic distortion and higher dc bus utilisation than the other two PWM methods.
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Au nanoparticles stabilized by poly(methyl methacrylate) (PMMA) were used as a catalyst to grow vertically aligned ZnO nanowires (NWs). The density of ZnO NWs with very uniform diameter was controlled by changing the concentration of Au-PMMA nanoparticles (NPs). The density was in direct proportion to the concentration of Au-PMMA NPs. Furthermore, the growth process of ZnO NWs using Au-PMMA NPs was systematically investigated through comparison with that using Au thin film as a catalyst. Au-PMMA NPs induced polyhedral-shaped bases of ZnO NWs separated from each other, while Au thin film formed a continuous network of bases of ZnO NWs. This approach provides a facile and cost-effective catalyst density control method, allowing us to grow high-quality vertically aligned ZnO NWs suitable for many viable applications.