Production of silica gel from residual rice husk ash

This paper presents a study on the production of silica gel in hydrothermal process using residual rice husk ash. Measurements of the chemical composition, X-ray diffraction, infrared spectroscopy, particle size distribution, and pozzolanic activity were carried out in order to characterize the obtained material, and the optimal silica gel was selected for use as a mineral additive in cement pastes. The compressive strengths were determined for cement pastes containing silica gel (0.0, 2.5 or 5% by mass) in different times. The results indicate that the mixtures containing silica gel showed improved mechanical behavior over all time periods evaluated.

Inertization of small-scale chemical wastes using iron phosphate glass

The viability of small-scale heavy-metal waste immobilization into iron phosphate glasses was investigated. Several waste forms containing different amounts of heavy-ion wastes were evaluated (5%, 10%, 15%, 20%, 26%, 33%, 40% and 50% by mass) and their X-ray diffraction patterns revealed that no crystallization occurred in glasses with waste concentrations up to 26%. The dissolution rates for all of the reported glass compositions (ca. 10-8 g cm-2 min-1) are similar to those reported for the materials most commonly used for waste vitrification. Iron phosphate glasses thus proved to be very useful for the immobilization of heavy-metal wastes, exhibiting good contention and chemical durability comparable to that of borosilicate glasses.

Modeling and Analysis of Noise and Interconnects for On-Chip Communication Link Design

This thesis considers modeling and analysis of noise and interconnects in onchip communication. Besides transistor count and speed, the capabilities of a modern design are often limited by on-chip communication links. These links typically consist of multiple interconnects that run parallel to each other for long distances between functional or memory blocks. Due to the scaling of technology, the interconnects have considerable electrical parasitics that affect their performance, power dissipation and signal integrity. Furthermore, because of electromagnetic coupling, the interconnects in the link need to be considered as an interacting group instead of as isolated signal paths. There is a need for accurate and computationally effective models in the early stages of the chip design process to assess or optimize issues affecting these interconnects. For this purpose, a set of analytical models is developed for on-chip data links in this thesis. First, a model is proposed for modeling crosstalk and intersymbol interference. The model takes into account the effects of inductance, initial states and bit sequences. Intersymbol interference is shown to affect crosstalk voltage and propagation delay depending on bus throughput and the amount of inductance. Next, a model is proposed for the switching current of a coupled bus. The model is combined with an existing model to evaluate power supply noise. The model is then applied to reduce both functional crosstalk and power supply noise caused by a bus as a trade-off with time. The proposed reduction method is shown to be effective in reducing long-range crosstalk noise. The effects of process variation on encoded signaling are then modeled. In encoded signaling, the input signals to a bus are encoded using additional signaling circuitry. The proposed model includes variation in both the signaling circuitry and in the wires to calculate the total delay variation of a bus. The model is applied to study level-encoded dual-rail and 1-of-4 signaling. In addition to regular voltage-mode and encoded voltage-mode signaling, current-mode signaling is a promising technique for global communication. A model for energy dissipation in RLC current-mode signaling is proposed in the thesis. The energy is derived separately for the driver, wire and receiver termination.

Exploring Adaptive Implementation of On-Chip Networks

As technology geometries have shrunk to the deep submicron regime, the communication delay and power consumption of global interconnections in high performance Multi- Processor Systems-on-Chip (MPSoCs) are becoming a major bottleneck. The Network-on- Chip (NoC) architecture paradigm, based on a modular packet-switched mechanism, can address many of the on-chip communication issues such as performance limitations of long interconnects and integration of large number of Processing Elements (PEs) on a chip. The choice of routing protocol and NoC structure can have a significant impact on performance and power consumption in on-chip networks. In addition, building a high performance, area and energy efficient on-chip network for multicore architectures requires a novel on-chip router allowing a larger network to be integrated on a single die with reduced power consumption. On top of that, network interfaces are employed to decouple computation resources from communication resources, to provide the synchronization between them, and to achieve backward compatibility with existing IP cores. Three adaptive routing algorithms are presented as a part of this thesis. The first presented routing protocol is a congestion-aware adaptive routing algorithm for 2D mesh NoCs which does not support multicast (one-to-many) traffic while the other two protocols are adaptive routing models supporting both unicast (one-to-one) and multicast traffic. A streamlined on-chip router architecture is also presented for avoiding congested areas in 2D mesh NoCs via employing efficient input and output selection. The output selection utilizes an adaptive routing algorithm based on the congestion condition of neighboring routers while the input selection allows packets to be serviced from each input port according to its congestion level. Moreover, in order to increase memory parallelism and bring compatibility with existing IP cores in network-based multiprocessor architectures, adaptive network interface architectures are presented to use multiple SDRAMs which can be accessed simultaneously. In addition, a smart memory controller is integrated in the adaptive network interface to improve the memory utilization and reduce both memory and network latencies. Three Dimensional Integrated Circuits (3D ICs) have been emerging as a viable candidate to achieve better performance and package density as compared to traditional 2D ICs. In addition, combining the benefits of 3D IC and NoC schemes provides a significant performance gain for 3D architectures. In recent years, inter-layer communication across multiple stacked layers (vertical channel) has attracted a lot of interest. In this thesis, a novel adaptive pipeline bus structure is proposed for inter-layer communication to improve the performance by reducing the delay and complexity of traditional bus arbitration. In addition, two mesh-based topologies for 3D architectures are also introduced to mitigate the inter-layer footprint and power dissipation on each layer with a small performance penalty.

Dieselmoottorisen kaupunkilinja-auton muuttaminen sarjahybridiajoneuvoksi

Tutkimus on pohjustusta Lappeenrannan teknillisen yliopiston Green Campus–hankkeessa tulevaisuudessa mahdollisesti rakennettavalle Cambus–hybridibussille ja siihen liittyvälle muutostyölle. Tässä tutkimuksessa käsitellään asioita, joita kohdataan kun tavallinen dieselkäyttöinen linja–auto muutetaan hybridiajoneuvoksi. Työ sisältää teoriaosuuden, jossa esitellään peruskomponentteja esimerkiksi moottoreiden ja energianvarastointitekniikoiden osalta sekä uusimpia kehityskohteita polttomoottoreiden osalta. Tutkimuksessa on myös vertailtu erilaisia hybridivaihtoehtoja sekä käsitelty mm. tasauspyörästön välityssuhteen ja vaihteiston vaikutusta bussin teoreettiseen suorituskykyyn. Tehdyn tutkimustyön perusteella on hahmoteltu eräs mahdollinen sarjahybridibussin voimansiirtolinja esimerkkikomponentteineen. Tutkimuksessa esitetään myös laskelmia järjestelmän teoreettisesta polttoaineenkulutuksesta jarrutusenergian talteenotto huomioiden perinteiseen kaupunkilinja-autoon verrattuna.

Energy expenditure in vocalizations of pigs under stress

Modern swine production faces many challenges nowadays, among which are productivity growth, meat quality improvement, decrease of environmental damage and reduction of cost production. Pigs spend energy to vocalizing, especially when they undergo stress. The waste of energy can increase the cost of production and lead to greater environmental damage. The goal of this study was to estimate the energy spent by pigs under the stress of castration and its effect on the animals' weight gain. Two groups of ten animals each were castrated, being one group with local anesthetic and the other without anesthetic. The piglets' vocalizations were recorded during different stages of the neutering process and then estimated of the amount of energy emitted during each vocalization. Afterwards, this energy was associated with the animals' weight gain. There was no difference in the total energy spent in both groups, since the energy used during the application of anesthetic was similar to the energy spent during the castration of the animals without anesthetic. There was also no correlation between energy spent and the animals' weight gain. It was possible to estimate the amount of energy emitted through vocalization. This energy spent by piglets in pain was greater than in other handling situations (contention, weighting and realease).

Uusia tulkintoja maailmanhistorian pahimmasta nälänhädästä

Kirjallisuusarvostelu

Energian talteenotto liikkuvassa raskaassa työkoneessa

Tämä työ on osa Integrated Serial and Parallel Hybrid Drives in Working Machines projektia. Työssä simuloidaan ja lasketaan energian palautuspotentiaalia raskaassa liikkuvassa työkoneessa. Työn alussa aihetta käsitellään yleisesti kirjallisuuskatsauksen muodossa. Tukkikurottaja valittiin simulointien ja laskennan kohteeksi. Työssä suoritettiin alustavat simuloinnit, joiden tarkoituksena oli varmistua, että palautettavaa energiaa on olemassa. Tulokset osoittavat, että energian palauttaminen on mahdollista. Mittaukset ovat osa työtä. Mitatut muuttujat ovat paineet ja pituudet hydraulisylintereistä, rungon kiihtyvyys, sekä kaikki CAN-väylään kytkettyjen antureiden mittaustiedot. Lopulliset simuloinnit perustuvat mitattuihin työkiertoihin. Työsylintereiden ja ajovoimansiirron tehotarpeet valittiin simulointien tarkasteltaviksi mittaussuureiksi. Mahdollinen palautettavan energian määrä eri työkierroissa on työn lopputulos. Tulokset osoittavat, että palautettavan energian määrä on talteenoton kannalta riittävä.

Multi-axis solutions in packaging machines in Europe

The objective of this thesis was to examine the potential of multi-axis solutions in packaging machines produced in Europe. The definition of a multi-axis solution in this study is a construction that uses a common DC bus power supply for different amplifiers running the axes and the intelligence is centralized into one unit. The cost structure of a packaging machine was gained from an automation research, which divided the machines according to automation categories. The automation categories were then further divided into different sub-components by evaluating the ratio of multi-axis solutions compared to other automation components in packaging machines. A global motion control study was used for further information. With the help of the ratio, an estimation of the potential of multi-axis solutions in each country and packaging machine sector was completed. In addition to the research, a specific questionnaire was sent to five companies to gain information about the present situation and possible trends in packaging machinery. The greatest potential markets are in Germany and Italy, which are also the largest producers of packaging machinery in Europe. The greatest growth in the next few years will be seen in Turkey where the annual growth rate equals the general machinery production rate in Asia. The greatest market potential of the Nordic countries is found in Sweden in 35th position on the list. According to the interviews, motion control products in packaging machines will retain their current power levels, as well as the number of axes in the future. Integrated machine safety features together with a universal programming language are the desired attributes of the future. Unlike generally in industry, the energy saving objectives are and will remain insignificant in the packaging industry.

Joukkoliikenteen koontikannan prosessien kehittäminen

Vuoden 2009 lopulla voimaan astuneet EU:n palvelusopimusasetus (PSA) ja kansallinen joukkoliikennelaki (869/2009) pakottavat avaamaan joukkoliikenteen markkinat kilpailulle koko Suomen alueella. Tästä johtuen Liikenne- ja viestintäministeriö on velvoittanut Liikenneviraston hankkimaan riittävän informaatiopohjan joukkoliikenteen kilpailutusten pohjaksi. Tämä pakottaa viraston uudistamaan bussipysäkkitiedon hallintansa ja -prosessinsa lähes kokonaan. Tämän työn tavoitteena oli selvittää, millaiset prosessit Liikenneviraston tulisi muodostaa, jotta tiedot jokaisen Suomen kunnan ja kaupungin katuverkon bussipysäkeistä saataisiin siirrettyä uuteen, kansalliseen joukkoliikenteen koontitietokantaan. Työssä tutkitaan, tarkastellaan ja kategorisoidaan Suomen kunnat ja kaupungit pysäkkitiedon hallinnoijan näkökulmasta. Tämän perusteella kehitetään vanhoja pysäkkitiedon prosesseja sekä luodaan uusia prosessimalleja pysäkkitiedon siirrolle ja päivitykselle. Jaottelun apuna käytetään kyselytutkimusta ja puhelinhaastatteluja. Kirjallisuusosa sisältää yleistä teoriaa prosesseista, niiden vaiheista ja kehittämisestä. Työn keskeisempänä tuloksena ovat prosessimallit siitä, miten pysäkkitiedon tulisi jatkossa siirtyä eri joukkoliikenneviranomaisilta Liikenneviraston kansalliseen koontikantaan. Lisäksi työssä huomattiin, että aktiivinen johtaminen ja yhteydenpito Liikenneviraston suunnalta ovat tärkeimmät edellytykset sille, että pysäkkitieto liikkuu ja tiedonsiirto paranee eri toimijoiden välillä.

Readout Electronics for Gas Electron Multiplier Detectors

The European Organization for Nuclear Research (CERN) operates the largest particle collider in the world. This particle collider is called the Large Hadron Collider (LHC) and it will undergo a maintenance break sometime in 2017 or 2018. During the break, the particle detectors, which operate around the particle collider, will be serviced and upgraded. Following the improvement in performance of the particle collider, the requirements for the detector electronics will be more demanding. In particular, the high amount of radiation during the operation of the particle collider sets requirements for the electronics that are uncommon in commercial electronics. Electronics that are built to function in the challenging environment of the collider have been designed at CERN. In order to meet the future challenges of data transmission, a GigaBit Transceiver data transmission module and an E-Link data bus have been developed. The next generation of readout electronics is designed to benefit from these technologies. However, the current readout electronics chips are not compatible with these technologies. As a result, in addition to new Gas Electron Multiplier (GEM) detectors and other technology, a new compatible chip is developed to function within the GEMs for the Compact Muon Solenoid (CMS) project. In this thesis, the objective was to study a data transmission interface that will be located on the readout chip between the E-Link bus and the control logic of the chip. The function of the module is to handle data transmission between the chip and the E-Link. In the study, a model of the interface was implemented with the Verilog hardware description language. This process was simulated by using chip design software by Cadence. State machines and operating principles with alternative possibilities for implementation are introduced in the E-Link interface design procedure. The functionality of the designed logic is demonstrated in simulation results, in which the implemented model is proven to be suitable for its task. Finally, suggestions that should be considered for improving the design have been presented.

Analysis of emergency braking performance with particular consideration of temperature effects on brakes

During vehicle deceleration due to braking there is friction between the lining surface and the brake drum or disc. In this process the kinetic energy of vehicle is turned into thermal energy that raises temperature of the components. The heating of the brake system in the course of braking is a great problem, because besides damaging the system, it may also affect the wheel and tire, which can cause accidents. In search of the best configuration that considers the true conditions of use, without passing the safety limits, models and formulations are presented with respect to the brake system, considering different braking conditions and kinds of brakes. Some modeling was analyzed using well-known methods. The flat plate model considering energy conservation was applied to a bus, using for this a computer program. The vehicle is simulated to undergo an emergency braking, considering the change of temperature on the lining-drum. The results include deceleration, braking efficiency, wheel resistance, normal reaction on the tires and the coefficient of adhesion. Some of the results were compared with dynamometer tests made by FRAS-LE and others were compared with track tests made by Mercedes-Benz. The convergence between the results and the tests is sufficient to validate the mathematical model. The computer program makes it possible to simulate the brake system performance in the vehicle. It assists the designer during the development phase and reduces track tests.

Integration of Electronic Commerce and Enterprise Systems

The necessity of EC (Electronic Commerce) and enterprise systems integration is perceived from the integrated nature of enterprise systems. The proven benefits of EC to provide competitive advantages to the organizations force enterprises to adopt and integrate EC with their enterprise systems. Integration is a complex task to facilitate seamless flow of information and data between different systems within and across enterprises. Different systems have different platforms, thus to integrate systems with different platforms and infrastructures, integration technologies, such as middleware, SOA (Service-Oriented Architecture), ESB (Enterprise Service Bus), JCA (J2EE Connector Architecture), and B2B (Business-to-Business) integration standards are required. Huge software vendors, such as Oracle, IBM, Microsoft, and SAP suggest various solutions to address EC and enterprise systems integration problems. There are limited numbers of literature about the integration of EC and enterprise systems in detail. Most of the studies in this area have focused on the factors which influence the adoption of EC by enterprise or other studies provide limited information about a specific platform or integration methodology in general. Therefore, this thesis is conducted to cover the technical details of EC and enterprise systems integration and covers both the adoption factors and integration solutions. In this study, many literature was reviewed and different solutions were investigated. Different enterprise integration approaches as well as most popular integration technologies were investigated. Moreover, various methodologies of integrating EC and enterprise systems were studied in detail and different solutions were examined. In this study, the influential factors to adopt EC in enterprises were studied based on previous literature and categorized to technical, social, managerial, financial, and human resource factors. Moreover, integration technologies were categorized based on three levels of integration, which are data, application, and process. In addition, different integration approaches were identified and categorized based on their communication and platform. Also, different EC integration solutions were investigated and categorized based on the identified integration approaches. By considering different aspects of integration, this study is a great asset to the architectures, developers, and system integrators in order to integrate and adopt EC with enterprise systems.

Design Space Exploration for MPSoC Architectures

Multiprocessor system-on-chip (MPSoC) designs utilize the available technology and communication architectures to meet the requirements of the upcoming applications. In MPSoC, the communication platform is both the key enabler, as well as the key differentiator for realizing efficient MPSoCs. It provides product differentiation to meet a diverse, multi-dimensional set of design constraints, including performance, power, energy, reconfigurability, scalability, cost, reliability and time-to-market. The communication resources of a single interconnection platform cannot be fully utilized by all kind of applications, such as the availability of higher communication bandwidth for computation but not data intensive applications is often unfeasible in the practical implementation. This thesis aims to perform the architecture-level design space exploration towards efficient and scalable resource utilization for MPSoC communication architecture. In order to meet the performance requirements within the design constraints, careful selection of MPSoC communication platform, resource aware partitioning and mapping of the application play important role. To enhance the utilization of communication resources, variety of techniques such as resource sharing, multicast to avoid re-transmission of identical data, and adaptive routing can be used. For implementation, these techniques should be customized according to the platform architecture. To address the resource utilization of MPSoC communication platforms, variety of architectures with different design parameters and performance levels, namely Segmented bus (SegBus), Network-on-Chip (NoC) and Three-Dimensional NoC (3D-NoC), are selected. Average packet latency and power consumption are the evaluation parameters for the proposed techniques. In conventional computing architectures, fault on a component makes the connected fault-free components inoperative. Resource sharing approach can utilize the fault-free components to retain the system performance by reducing the impact of faults. Design space exploration also guides to narrow down the selection of MPSoC architecture, which can meet the performance requirements with design constraints.

Moottorin paikkasäädön toteutus dsPIC-ohjaimella

Työssä suunniteltiin nostinsimulaattorin z-akselin suuntaiselle moottorille paikkasäätö ja sen ohjaus CAN-väylää pitkin. Työ toteutettiin projektiryhmässä, jossa eri henkilöt vastasivat eri osa-alueista. CAN-kommunikointi saatiin toimimaan ja lisäksi moottorilta pystyttiin lukemaan paikkatieto talteen. Moottorin säätö jäi vielä puuttumaan.