High Speed FPGA-based implementations of Delayed-LMS filters

A variation of the least means squares (LMS) algorithm, called the delayed LMS (DLMS) algorithm is an ideally suited to achieve highly pipelined, adaptive digital filter implementations. The paper presents an efficient method of determining the delays in the DLMS filter and then transferring these delays using retiming in order to achieve fully pipelined circuit architectures for FPGA implementation. The method has been used to derive a series of retimed delayed LMS (RDLMS) architectures, which considerable reduce the number of delays and convergence time and give superior performance in terms of throughput rate when compared to previous work. Three circuit architectures and three hardware shared versions are presented which have been implemented using the Virtex-II FPGA technology resulting in a throughout rate of 182 Msample/s.

Estimation of speed of sound of ionic liquids using surface tensions and densities: A volume based approach

The limited availability of experimental data and their quality have been preventing the development of predictive methods and Computer Aided Molecular Design (CAMD) of ionic liquids (ILs). Based on experimental speed of sound data collected from the literature, the inter-relationship of surface tension (s), density (?), and speed of sound (u) has been examined for imidazolium based ILs containing hexafluorophosphate (PF6), tetrafluoroborate (BF4), bis(trifluoromethanesulphonyl) amide (NTf2), methyl sulphate (MeSO4), ethyl sulphate (EtSO4), and trifluoromethanesulphonate (CF3SO3) anions, covering wide ranges of temperature, 278.15–343.15 K and speed of sound, 1129.0–1851.0 m s-1. The speed of sound was correlated with a modified Auerbach's relation, by using surface tension and density data obtained from volume based predictive methods previously proposed by the authors. It is shown that a good agreement with literature data is obtained. For 133 data points of 14 ILs studied a mean percent deviation (MPD) of 1.96% with a maximum deviation inferior to 5% was observed. The correlations developed here can thus be used to evaluate the speeds of sound of new ionic liquids.

Area-efficient high-speed 3D DWT processor architecture

An area-efficient high-throughput architecture based on distributed arithmetic is proposed for 3D discrete wavelet transform (DWT). The 3D DWT processor was designed in VHDL and mapped to a Xilinx Virtex-E FPGA. The processor runs up to 85 MHz, which can process the five-level DWT analysis of a 128 x 128 x 128 fMRI volume image in 20 ms.