Efficient advanced encryption standard implementation using lookup and normal basis

A new type of advanced encryption standard (AES) implementation using a normal basis is presented. The method is based on a lookup technique that makes use of inversion and shift registers, which leads to a smaller size of lookup for the S-box than its corresponding implementations. The reduction in the lookup size is based on grouping sets of inverses into conjugate sets which in turn leads to a reduction in the number of lookup values. The above technique is implemented in a regular AES architecture using register files, which requires less interconnect and area and is suitable for security applications. The results of the implementation are competitive in throughput and area compared with the corresponding solutions in a polynomial basis.

Mixed radix Reed-Muller expansions

The choice of radix is crucial for multi-valued logic synthesis. Practical examples, however, reveal that it is not always possible to find the optimal radix when taking into consideration actual physical parameters of multi-valued operations. In other words, each radix has its advantages and disadvantages. Our proposal is to synthesise logic in different radices, so it may benefit from their combination. The theory presented in this paper is based on Reed-Muller expansions over Galois field arithmetic. The work aims to firstly estimate the potential of the new approach and to secondly analyse its impact on circuit parameters down to the level of physical gates. The presented theory has been applied to real-life examples focusing on cryptographic circuits where Galois Fields find frequent application. The benchmark results show the approach creates a new dimension for the trade-off between circuit parameters and provides information on how the implemented functions are related to different radices.

Dynamic global security-aware synthesis using System-C

A dynamic global security-aware synthesis flow using the SystemC language is presented. SystemC security models are first specified at the system or behavioural level using a library of SystemC behavioural descriptions which provide for the reuse and extension of security modules. At the core of the system is incorporated a global security-aware scheduling algorithm which allows for scheduling to a mixture of components of varying security level. The output from the scheduler is translated into annotated nets which are subsequently passed to allocation, optimisation and mapping tools for mapping into circuits. The synthesised circuits incorporate asynchronous secure power-balanced and fault-protected components. Results show that the approach offers robust implementations and efficient security/area trade-offs leading to significant improvements in turnover.

Applying an XC6200 to real-time image processing

This implementation of a two-dimensional discrete cosine transform demonstrates the development of a suitable architectural style for a specific technology-in this case, the Xilinx XC6200 FPGA series. The design exploits distributed arithmetic, parallelism, and pipelining to achieve a high-performance custom-computing implementation.

Discovery of Novel Allosteric Modulators of Metabotropic Glutamate Receptor Subtype 5 Reveals Chemical and Functional Diversity and In Vivo Activity in Rat Behavioral Models of Anxiolytic and Antipsychotic Activity

Modulators of metabotropic glutamate receptor subtype 5 (mGluR5) may provide novel treatments for multiple central nervous system (CNS) disorders, including anxiety and schizophrenia. Although compounds have been developed to better understand the physiological roles of mGluR5 and potential usefulness for the treatment of these disorders, there are limitations in the tools available, including poor selectivity, low potency, and limited solubility. To address these issues, we developed an innovative assay that allows simultaneous screening for mGluR5 agonists, antagonists, and potentiators. We identified multiple scaffolds that possess diverse modes of activity at mGluR5, including both positive and negative allosteric modulators (PAMs and NAMs, respectively). 3-Fluoro-5-(3-(pyridine-2-yl)-1,2,4-oxadiazol-5-yl) benzonitrile (VU0285683) was developed as a novel selective mGluR5 NAM with high affinity for the 2-methyl-6-(phenyl-ethynyl)-pyridine (MPEP) binding site. VU0285683 had anxiolytic-like activity in two rodent models for anxiety but did not potentiate phen-cyclidine-induced hyperlocomotor activity. (4-Hydroxypiperidin-1-yl)(4-phenylethynyl) phenyl) methanone (VU0092273) was identified as a novel mGluR5 PAM that also binds to the MPEP site. VU0092273 was chemically optimized to an orally active analog, N-cyclobutyl-6-((3-fluorophenyl) ethynyl) nicotinamide hydrochloride (VU0360172), which is selective for mGluR5. This novel mGluR5 PAM produced a dose-dependent reversal of amphetamine-induced hyperlocomotion, a rodent model predictive of antipsychotic activity. Discovery of structurally and functionally diverse allosteric modulators of mGluR5 that demonstrate in vivo efficacy in rodent models of anxiety and antipsychotic activity provide further support for the tremendous diversity of chemical scaffolds and modes of efficacy of mGluR5 ligands. In addition, these studies provide strong support for the hypothesis that multiple structurally distinct mGluR5 modulators have robust activity in animal models that predict efficacy in the treatment of CNS disorders.

Managing SMT Resource Usage through Speculative Instruction Window Weighting

Simultaneous multithreading processors dynamically share processor resources between multiple threads. In general, shared SMT resources may be managed explicitly, for instance, by dynamically setting queue occupation bounds for each thread as in the DCRA and Hill-Climbing policies. Alternatively, resources may be managed implicitly; that is, resource usage is controlled by placing the desired instruction mix in the resources. In this case, the main resource management tool is the instruction fetch policy which must predict the behavior of each thread (branch mispredictions, long-latency loads, etc.) as it fetches instructions.

Fairness Metrics for Multi-Threaded Processors

Multi-threaded processors execute multiple threads concurrently in order to increase overall throughput. It is well documented that multi-threading affects per-thread performance but, more importantly, some threads are affected more than others. This is especially troublesome for multi-programmed workloads. Fairness metrics measure whether all threads are affected equally. However defining equal treatment is not straightforward. Several fairness metrics for multi-threaded processors have been utilized in the literature, although there does not seem to be a consensus on what metric does the best job of measuring fairness. This paper reviews the prevalent fairness metrics and analyzes their main properties. Each metric strikes a different trade-off between fairness in the strict sense and throughput. We categorize the metrics with respect to this property. Based on experimental data for SMT processors, we suggest using the minimum fairness metric in order to balance fairness and throughput.

A profile-based tool for finding pipeline parallelism in sequential programs

Traditional static analysis fails to auto-parallelize programs with a complex control and data flow. Furthermore, thread-level parallelism in such programs is often restricted to pipeline parallelism, which can be hard to discover by a programmer. In this paper we propose a tool that, based on profiling information, helps the programmer to discover parallelism. The programmer hand-picks the code transformations from among the proposed candidates which are then applied by automatic code transformation techniques.

This paper contributes to the literature by presenting a profiling tool for discovering thread-level parallelism. We track dependencies at the whole-data structure level rather than at the element level or byte level in order to limit the profiling overhead. We perform a thorough analysis of the needs and costs of this technique. Furthermore, we present and validate the belief that programs with complex control and data flow contain significant amounts of exploitable coarse-grain pipeline parallelism in the program’s outer loops. This observation validates our approach to whole-data structure dependencies. As state-of-the-art compilers focus on loops iterating over data structure members, this observation also explains why our approach finds coarse-grain pipeline parallelism in cases that have remained out of reach for state-of-the-art compilers. In cases where traditional compilation techniques do find parallelism, our approach allows to discover higher degrees of parallelism, allowing a 40% speedup over traditional compilation techniques. Moreover, we demonstrate real speedups on multiple hardware platforms.