Aeroacoustic source measurement methods for characterizing the sound generated by ducted flow devices with higher-order modes.

The International Organization for Standardization (ISO) method 5136 is widely used in industry and academia to determine the sound power radiated into a duct by fans and other flow devices. The method involves placing the device at the center of a long cylindrical duct with anechoic terminations at each end to eliminate reflections. A single off-axis microphone is used on the inlet and outlet sides that can theoretically capture the plane-wave mode amplitudes but this does not provide enough information to fully account for higher-order modes. In this study, the "two-port" source model is formulated to include higher-order modes and applied for the first three modes. This requires six independent surface pressure measurements on each side or "port." The resulting experimental set-up is much shorter than the ISO rig and does not require anechoic terminations. An array of six external loudspeaker sources is used to characterize the passive part of the two-port model and the set-up provides a framework to account for transmission of higher-order modes through a fan. The relative importance of the higher-order modes has been considered and their effect on inaccuracies when using the ISO method to find source sound power has been analyzed.

Effect of bandgap narrowing on performance of modern power devices

The effect of the bandgap narrowing (BGN) on performance of power devices is investigated in detail in this paper. The analysis reveals that the change in the energy band structure caused by BGN can strongly affect the conductivity modulation of the bipolar devices resulting in a completely different performance. This is due to the modified injection efficiency under high-level injection conditions. Using a comprehensive analysis of the injection efficiency in a p-n junction, an analytical model for this phenomenon is developed. BGN model tuning has been proved to be essential in accurately predicting the performance of a lateral insulated-gate bipolar transistor (IGBT). Other devices such as p-i-n diodes or punch-through IGBTs are significantly affected by the BGN, while others, such as field-stop IGBTs or power MOSFETs, are only marginally affected. © 2013 IEEE.

Computational engineering design for micro-scale combustion devices: A thermally improved configuration

A multi-objective design optimisation study has been carried out with the objectives to improve the overall efficiency of the device and to reduce the fuel consumption for the proposed micro-scale combustor design configuration. In a previous study we identified the topology of the combustion chamber that produced improved behaviour of the device in terms of the above design criteria. We now extend our design approach, and we propose a new configuration by the addition of a micro-cooling channel that will improve the thermal behaviour of the design as previously suggested in literature. Our initial numerical results revealed an improvement of 2.6% in the combustion efficiency when we applied the micro-cooling channel to an optimum design configuration we identified from our earlier multi-objective optimisation study, and under the same operating conditions. The computational modelling of the combustion process is implemented in the commercial computational fluid dynamics package ANSYS-CFX using Finite Rate Chemistry and a single step hydrogen-air reaction. With this model we try to balance good accuracy of the combustion solution and at the same time practicality within the context of an optimisation process. The whole design system comprises also the ANSYS-ICEM CFD package for the automatic geometry and mesh generation and the Multi-Objective Tabu Search algorithm for the design space exploration. We model the design problem with 5 geometrical parameters and 3 operational parameters subject to 5 design constraints that secure practicality and feasibility of the new optimum design configurations. The final results demonstrate the reliability and efficiency of the developed computational design system and most importantly we assess the practicality and manufacturability of the revealed optimum design configurations of micro-combustor devices. Copyright © 2013 by ASME.

Direct temperature mapping of nanoscale plasmonic devices.

Side by side with the great advantages of plasmonics in nanoscale light confinement, the inevitable ohmic loss results in significant joule heating in plasmonic devices. Therefore, understanding optical-induced heat generation and heat transport in integrated on-chip plasmonic devices is of major importance. Specifically, there is a need for in situ visualization of electromagnetic induced thermal energy distribution with high spatial resolution. This paper studies the heat distribution in silicon plasmonic nanotips. Light is coupled to the plasmonic nanotips from a silicon nanowaveguide that is integrated with the tip on chip. Heat is generated by light absorption in the metal surrounding the silicon nanotip. The steady-state thermal distribution is studied numerically and measured experimentally using the approach of scanning thermal microscopy. It is shown that following the nanoscale heat generation by a 10 mW light source within a silicon photonic waveguide the temperature in the region of the nanotip is increased by ∼ 15 °C compared with the ambient temperature. Furthermore, we also perform a numerical study of the dynamics of the heat transport. Given the nanoscale dimensions of the structure, significant heating is expected to occur within the time frame of picoseconds. The capability of measuring temperature distribution of plasmonic structures at the nanoscale is shown to be a powerful tool and may be used in future applications related to thermal plasmonic applications such as control heating of liquids, thermal photovoltaic, nanochemistry, medicine, heat-assisted magnetic memories, and nanolithography.

High resolution direct measurement of temperature distribution in silicon nanophotonics devices.

Following the miniaturization of photonic devices and the increase in data rates, the issues of self heating and heat removal in active nanophotonic devices should be considered and studied in more details. In this paper we use the approach of Scanning Thermal Microscopy (SThM) to obtain an image of the temperature field of a silicon micro ring resonator with sub-micron spatial resolution. The temperature rise in the device is a result of self heating which is caused by free carrier absorption in the doped silicon. The temperature is measured locally and directly using a temperature sensitive AFM probe. We show that this local temperature measurement is feasible in the photonic device despite the perturbation that is introduced by the probe. Using the above method we observed a significant self heating of about 10 degrees within the device.

Nanoscale temperature mapping of photonic and plasmonic devices

We experimentally demonstrate nanoscale thermal mapping of light induced heat in photonic and plasmonic devices using a thermocouple AFM tip. Numerical simulations results and nanoscale temperature measurements are presented and discussed. © OSA 2013.

Determination of PAH, PCB, and OCP in water from the Three Gorges Reservoir accumulated by semipermeable membrane devices (SPMD)

Bioavailable water concentrations of polycyclic aromatic hydrocarbons (PAH), polychlorinated biphenyls (PCB) and organochlorine pesticides (OCP) were measured in the water column from Three Gorges Reservoir (TGR) collected in May 2008 using semipermeable membrane devices (SPMDs). The sampling sites spanned the whole reservoir from the upstream Chongqing to the great dam covering more than 600 km long distance with water flow velocities ranging from <0.05 to 1.5 m s(-1). This is the first experience of SPMD application in the biggest reservoir in the world. The results of water sampling rates based on performance reference compounds (PRC) were tested to be significantly correlated with water flow velocities in the big river. Results of back-calculated aqueous concentrations based on PRC showed obvious regional variations of PAH, PCB and OCP levels in the reservoir. Total PAH ranged from 13.8 to 97.2 ng L-1, with the higher concentrations occurring in the region of upstream and near the dam. Phenanthrene, fluoranthene, pyrene and chrysene were the predominant PAH compounds in TGR water. Total PCB ranged from 0.08 to 0.51 ng L-1, with the highest one occurring in the region near the dam. PCB 28, 52, 101, 138, 153, 180, 118 were the most abundant PCB congeners in the water. The total OCP ranged from 2.33 to 3.60 ng L-1 and the levels showed homogenous distribution in the whole reservoir. HCH, DDT and HCB, PeCB were the major compounds of OCP fingerprints. Based on water quality criteria, the TGR water could be designated as being polluted by HCB and PAH. Data on PAH, PCB and OCP concentrations found in this survey can be used as reference levels for future POP monitoring programmes in TGR. (C) 2009 Elsevier Ltd. All rights reserved.

Assembly and inspection of liquid crystal on silicon devices

Liquid crystal on silicon (LCOS) is one of the most exciting technologies, combining the optical modulation characteristics of liquid crystals with the power and compactness of a silicon backplane. The objective of our work is to improve cell assembly and inspection methods by introducing new equipment for automated assembly and by using an optical inspection microscope. A Suss-MicroTec Universal device bonder is used for precision assembly and device packaging and an Olympus BX51 high resolution microscope is employed for device inspection. © 2009 Optical Society of America.

Crosstalk reduction in holographic wavelength selective switches based on phase-only LCOS devices

A method to reduce crosstalk is proposed for holographic wavelength selective switches (WSSs) using a customized merit function. A reduction in crosstalk >8 dB is measured when multicasting with a phase-only LCOS device. © OSA 2014.

Ni(Pt)-silicide contacts on CMOS devices: Impact of substrate nature and Pt concentration on the phase formation

Ni silicides used as contacts in source/drain and gate of advanced CMOS devices were analyzed by atom probe tomography (APT) at atomic scale. These measurements were performed on 45 nm nMOS after standard self-aligned silicide (salicide) process using Ni(5 at.% Pt) alloy. After the first annealing (RTA1), δ-Ni2Si was the only phase formed on gate and source/drain while, after the second annealing (RTA2), two different Ni silicides have been formed: NiSi on the gate and δ-Ni2Si on the source and drain. This difference between source/drain and gate regions in nMOS devices has been related to the Si substrate nature (poly or mono-crystalline) and to the size of the contact. In fact, NiSi seems to have difficulties to nucleate in the narrow source/drain contact on mono-crystalline Si. The results have been compared to analysis performed on 28 nm nMOS where the Pt concentration is higher (10 at.% Pt). In this case, θ-Ni2Si is the first phase to form after RTA1 and NiSi is then formed at the same time on source (or drain) and gate after RTA2. The absence of the formation of NiSi from δ-Ni 2Si/Si(1 0 0) interface compared to θ-Ni2Si/Si(1 0 0) interface could be related to the difference of the interface energies. The redistributions of As and Pt in different silicides and interfaces were measured and discussed. In particular, it has been evidenced that Pt redistributions obtained on both 45 and 28 nm MOS transistors correspond to respective Pt distributions measured on blanket wafers. © 2013 Elsevier B.V. All rights reserved.

Effect of surface treatment of GaN based light emitting diode wafers on the leakage current of light emitting diode devices

To form low-resistance Ohmic contact to p-type GaN, InGaN/GaN multiple quantum well light emitting diode wafers are treated with boiled aqua regia prior to Ni/Au (5 nm/5 nm) film deposition. The surface morphology of wafers and the current-voltage characteristics of fabricated light emitting diode devices are investigated. It is shown that surface treatment with boiled aqua regia could effectively remove oxide from the surface of the p-GaN layer, and reveal defect-pits whose density is almost the same as the screw dislocation density estimated by x-ray rocking curve measurement. It suggests that the metal atoms of the Ni/Au transparent electrode of light emitting diode devices may diffuse into the p-GaN layer along threading dislocation lines and form additional leakage current channels. Therefore, the surface treatment time with boiled aqua regia should not be too long so as to avoid the increase of threading dislocation-induced leakage current and the degradation of electrical properties of light emitting diodes

Analysis of lateral current spreading in solar cell devices by spatially-resolved electroluminescence

Spatially-resolved electroluminescence (EL) images from solar cells contain information of local current distribution. By theoretical analysis of the EL intensity distribution, the current density distribution under a certain current bias and the sheet resistance can be obtained quantitatively. Two-dimensional numerical simulation of the current density distribution is employed to a GaInP cell, which agrees very well with the experimental results. A reciprocity theorem for current spreading is found and used to interpret the EL images from the viewpoint of current extraction. The optimization of front electrodes is discussed based on the results. (C) 2010 American Institute of Physics. [doi:10.1063/1.3431390]

Compact non-binary fast adders using single-electron devices

This paper proposes compact adders that are based on non-binary redundant number systems and single-electron (SE) devices. The adders use the number of single electrons to represent discrete multiple-valued logic state and manipulate single electrons to perform arithmetic operations. These adders have fast speed and are referred as fast adders. We develop a family of SE transfer circuits based on MOSFET-based SE turnstile. The fast adder circuit can be easily designed by directly mapping the graphical counter tree diagram (CTD) representation of the addition algorithm to SE devices and circuits. We propose two design approaches to implement fast adders using SE transfer circuits the threshold approach and the periodic approach. The periodic approach uses the voltage-controlled single-electron transfer characteristics to efficiently achieve periodic arithmetic functions. We use HSPICE simulator to verify fast adders operations. The speeds of the proposed adders are fast. The numbers of transistors of the adders are much smaller than conventional approaches. The power dissipations are much lower than CMOS and multiple-valued current-mode fast adders. (C) 2009 Elsevier Ltd. All rights reserved.