955 resultados para VLSI CAD
Resumo:
A neonatal temperature monitoring system operating in subthreshold regime that utilizes time mode signal processing is presented. Resistance deviations in a thermistor due to temperature variations are converted to delay variations that are subsequently quantized by a Delay measurement unit (DMU). The DMU does away with the need for any analog circuitry and is synthesizable entirely from digital logic. An FPGA implementation of the system demonstrates the viability of employing time mode signal processing, and measured results show that temperature resolution better than 0.1 degrees C can be achieved using this approach.
Resumo:
A logic gate-based digital frequency multiplication technique for low-power frequency synthesis is presented. The proposed digital edge combining approach offers broadband operation with low-power and low-area advantages and is a promising candidate for low-power frequency synthesis in deep submicrometer CMOS technologies. Chip prototype of the proposed frequency multiplication-based 2.4-GHz binary frequency-shift-keying (BFSK)/amplitude shift keying (ASK) transmitter (TX) was fabricated in 0.13-mu m CMOS technology. The TX achieves maximum data rates of 3 and 20 Mb/s for BFSK and ASK modulations, respectively, consuming a 14-mA current from 1.3 V supply voltage. The corresponding energy efficiencies of the TX are 3.6 nJ/bit for BFSK and 0.91 nJ/bit for ASK modulations.
Resumo:
Minimizing energy consumption is of utmost importance in an energy starved system with relaxed performance requirements. This brief presents a digital energy sensing method that requires neither a constant voltage reference nor a time reference. An energy minimizing loop uses this to find the minimum energy point and sets the supply voltage between 0.2 and 0.5 V. Energy savings up to 1275% over existing minimum energy tracking techniques in the literature is achieved.
Resumo:
Routing is a very important step in VLSI physical design. A set of nets are routed under delay and resource constraints in multi-net global routing. In this paper a delay-driven congestion-aware global routing algorithm is developed, which is a heuristic based method to solve a multi-objective NP-hard optimization problem. The proposed delay-driven Steiner tree construction method is of O(n(2) log n) complexity, where n is the number of terminal points and it provides n-approximation solution of the critical time minimization problem for a certain class of grid graphs. The existing timing-driven method (Hu and Sapatnekar, 2002) has a complexity O(n(4)) and is implemented on nets with small number of sinks. Next we propose a FPTAS Gradient algorithm for minimizing the total overflow. This is a concurrent approach considering all the nets simultaneously contrary to the existing approaches of sequential rip-up and reroute. The algorithms are implemented on ISPD98 derived benchmarks and the drastic reduction of overflow is observed. (C) 2014 Elsevier Inc. All rights reserved.
Resumo:
Zircon has been recognized as the unaltered part of the Earth's history which preserves nearly 4 billion year record of earth's evolution. Zircon preserves igneous and metamorphic processes during its formation and remains unaffected by sedimentary processes and crustal recycling. U-Pb and Lu-Hf in zircon work as geochronometer and geochemical tracer respectively. Zircon provide valuable information about the source composition of the rocks and the intrinsic details of an unseen crust-mantle processes. The world wide data of U-Pb and Lu-Hf isotope systems in zircon reveal crustal evolution through geological history. Moreover, the U-Pb age pattern of zircons show distinct peaks attributed to preservation of crustal rocks or mountain building during supercontinent assembly. The histogram of continental crust preservation shows that nearly one-third of continental crust was formed during the Archean, almost 20% was formed during Paleoproterozoic and 14% in last 400 Ma.
Resumo:
Support vector machines (SVM) are a popular class of supervised models in machine learning. The associated compute intensive learning algorithm limits their use in real-time applications. This paper presents a fully scalable architecture of a coprocessor, which can compute multiple rows of the kernel matrix in parallel. Further, we propose an extended variant of the popular decomposition technique, sequential minimal optimization, which we call hybrid working set (HWS) algorithm, to effectively utilize the benefits of cached kernel columns and the parallel computational power of the coprocessor. The coprocessor is implemented on Xilinx Virtex 7 field-programmable gate array-based VC707 board and achieves a speedup of upto 25x for kernel computation over single threaded computation on Intel Core i5. An application speedup of upto 15x over software implementation of LIBSVM and speedup of upto 23x over SVMLight is achieved using the HWS algorithm in unison with the coprocessor. The reduction in the number of iterations and sensitivity of the optimization time to variation in cache size using the HWS algorithm are also shown.
Resumo:
In gross motion of flexible one-dimensional (1D) objects such as cables, ropes, chains, ribbons and hair, the assumption of constant length is realistic and reasonable. The motion of the object also appears more natural if the motion or disturbance given at one end attenuates along the length of the object. In an earlier work, variational calculus was used to derive natural and length-preserving transformation of planar and spatial curves and implemented for flexible 1D objects discretized with a large number of straight segments. This paper proposes a novel idea to reduce computational effort and enable real-time and realistic simulation of the motion of flexible 1D objects. The key idea is to represent the flexible 1D object as a spline and move the underlying control polygon with much smaller number of segments. To preserve the length of the curve to within a prescribed tolerance as the control polygon is moved, the control polygon is adaptively modified by subdivision and merging. New theoretical results relating the length of the curve and the angle between the adjacent segments of the control polygon are derived for quadratic and cubic splines. Depending on the prescribed tolerance on length error, the theoretical results are used to obtain threshold angles for subdivision and merging. Simulation results for arbitrarily chosen planar and spatial curves whose one end is subjected to generic input motions are provided to illustrate the approach. (C) 2016 Elsevier Ltd. All rights reserved.
Resumo:
El objetivo del presente trabajo fue evaluar el efecto de la inclusión de harina de Marango (Moringa oleifera) en dietas para conejos de engorde y su efecto en el comportamiento productivo. Se utilizaron 36 conejos de camadas homogéneas con 37 d de edad, de las razas Neozelandés (18) y California (18) con pesos iniciales promedio de 554 g (133.8), los cuales fueron distribuidos en igual proporción de razas y sexos, en un Diseño Completamente al Azar con tres tratamientos: Tl: Concentrado Comercial, T2: Concentrado Isométrico, T3: Concentrado lsoprotéico. Las variables estudiadas fueron: consumo de alimento diario (CAD), ganancia media diaria (GMD), índice de conversión alimenticia (!CA), digestibilidad aparente de la materia seca (DMS), peso final (PF). Se realizó análisis de varianza y comparaciones de medias con la Prueba de Tukey utilizando el paquete estadístico MINITAB~:Ver. 12.0. Los resultados indican que para el CAD no se encontró diferencia significativa (P>0.05) siendo los valores promedio de 11 1.73g d"1 respectivamente. Sin embargo, para la GMD y la DMS se encontró diferencias (P
Resumo:
The paper describes a semianalytic slope delay model for CMOS switch-level timing verification. It is characterised by classification of the effects of the input slope, internal size and load capacitance of a logic gate on delay time, and then the use of a series of carefully chosen analytic functions to estimate delay times under different circumstances. In the field of VLSI analysis, this model achieves improvements in speed and accuracy compared with conventional approaches to transistor-level and switch-level simulation.
Resumo:
概要论述了微电子机械系统的计算机辅助设计和模拟过程,分析了MEMS CAD系统所应具有的主要内容和系统模拟中的关键问题,讨论了目前经常采用的各种模拟系 统的模拟形式和应 用范围。并结合静电微马达与微米/纳米镊子实例,分析了模块化的CAD软件结构形式以及所用MEMS材料的数据库建立和应用连接,所提出并采用的开发方式适用于微传感器及微执行器等微系统器件的设计与模拟。