The investigation of sweeping speed on the magnetization of a 2 inches diameter YBa2Cu3O7-δ thin film with the circular-type magnetic flux pump

A circular-type magnetic flux pump (CTMFP) device was built to study the flux dynamics on a 2-inch-diameter YBCO thin film. This CTMFP is composed of two CTMFP coils, with each CTMFP coil containing concentric three-phase windings and a dc winding. We connected the three-phase windings to the output of a commercial inverter. By changing the output frequency of the inverter, the sweeping speed of the circular-shaped travelling magnetic wave can be changed. The connection of the phase coils follows the forward consequence, so that the circular-shaped travelling magnetic wave travels inward to the center. The output frequency f was changed from f = 0.01 to 1000.0 Hz. The YBCO sample was sandwiched between the two CTMFP coils to experience the circular-shaped travelling magnetic wave. It was found that the increase of the flux density in the center of the film is independent of the sweeping frequency. In high frequency f = 1000.0Hz, even if the waveform had changed a lot, the increment is still the same as in low frequencies. © 2012 IEEE.

Use of a high-temperature superconducting coil for magnetic energy storage

A high temperature superconducting magnetic energy storage device (SMES) has been realised using a 350 m-long BSCCO tape wound as a pancake coil. The coil is mounted on a cryocooler allowing temperatures down to 17.2 K to be achieved. The temperature dependence of coil electrical resistance R(T) shows a superconducting transition at T 102.5 K. Measurements of the V(I) characteristics were performed at several temperatures between 17.2 K and 101.5 K to obtain the temperature dependence of the critical current (using a 1 νV/cm criterion). Critical currents were found to exceed 100 A for T < 30 K. An electronic DC-DC converter was built in order to control the energy flow in and out of the superconducting coil. The converter consists of a MOS transistor bridge switching at a 80 kHz frequency and controlled with standard Pulse Width Modulation (PWM) techniques. The system was tested using a 30 V squared wave power supply as bridge input voltage. The coil current, the bridge input and output voltages were recorded simultaneously. Using a 10 A setpoint current in the superconducting coil, the whole system (coil + DC-DC converter) can provide a stable output voltage showing uninterruptible power supply (UPS) capabilities over 1 s. © 2006 IOP Publishing Ltd.

A study of converter rating for brushless DFIG wind turbines

This paper studies the converter rating requirement of a Brushless Doubly-Fed Induction Generator for wind turbine applications by considering practical constraints such as generator torque-speed requirement, reactive power management and grid low-voltage ride-through (LVRT). Practical data have been used to obtain a realistic system model of a Brushless DFIG wind turbine using steady-state and dynamic models. A converter rating optimization is performed based on the given constraints. The converter current and voltage requirements are examined and the resulting inverter rating is compared to optimization algorithm results. In addition, the effects of rotor leakage inductance on LVRT performance and hence converter rating is investigated.

A Fully Integrated 900-MHz Passive RFID Transponder Front End With Novel Zero-Threshold RF-DC Rectifier

This paper presents a fully integrated CMOS analog front end for a passive 900-MHz radio-frequency identification (RFID) transponder. The power supply in this front end is generated from the received RF electromagnetic energy by using an RF-dc voltage rectifier. In order to improve the compatibility with standard CMOS technology, Schottky diodes in conventional RF-dc rectifiers are replaced by diode-connected MOS transistors with zero threshold. Meanwhile, theoretical analyses for the proposed rectifier are provided and verified by both simulation and measurement results. The design considerations of the pulsewidth-modulation (PWM) demodulator and the backscatter modulator in the front end are also discussed for low-power applications. The proposed front end is implemented in a 0.35-mu m 2P4M CMOS technology. The whole chip occupies a die area of 490 x 780 mu m(2) and consumes only 2.1 mu W in reading mode under a self-generated 1.5-V supply voltage. The measurement results show that the proposed rectifier can properly operate with a - 14.7-dBm input RF power at a power conversion efficiency of 13.0%. In the proposed RFID applications, this sensitivity corresponds to 10.88-m communication distance at 4-W equivalent isotropically radiated power from a reader base station.

一个易于系统集成的变步长反馈数字DC-DC变换模块

提出了一种采用单比较器变步长反馈控制和占空比抖动方法的数字DC-DC变换模块。它用6位二进制分辨率占空比的PWM信号实现了7位的电压分辨率。变步长反馈控制的使用使得它具有比恒定步长方案更好的动态性能，而且没有过多增加控制器的复杂度。在1MHz的开关频率下，控制器自身功耗小于0.5mW（不含功率开关及驱动部分）。由于电路的模拟部分极少，因此易与数字系统进行单芯片集成。

HIRFL—CSR数字电源控制模块的设计

介绍了一种基于TMS320C6713和FPGA的数字电源控制模块,给出了模块的硬件组成和软件设计。该模块作为一种通用的控制平台,可以根据现场需要来设置相应的参数,实现直流/脉冲电源的控制。测试表明该模块有很高的控制精度,处理能力强,便于网络控制。

HIRFL-CSR二极磁铁电源的研制；Development of Power Supply for HIRFL-CSR Dipole Magnet

研制了兰州重离子加速器冷却储存环(HIRFL-CSR)二极磁铁电源,提出了一种基于晶闸管相控整流技术和IGBT脉宽调制(PWM)变换技术的同步加速器二极磁铁电源的设计方案,分析、仿真了其工作原理,并设计、生产了1套完整的电源样机。经现场试验、长期运行及测试,电流稳定度<±5×10-5/8h,跟踪精度<±2×10-4,电流纹波<1×10-5。该方案满足HIRFL-CSR二极磁铁对电源技术指标的要求。

CSR电源调节器硬件平台设计

HIRFL-CSR（Heavy Ion Research Facility at LanZhou-Cooling Storage Ring兰州重离子冷却储存环）是国家重大科学工程，其控制系统是一个庞大的系统，由许多分控制系统组成，磁场电源控制系统是CSR控制系统中很重要的一部分。加速器运行的所有过程都为电源所控制，所以我们的控制系统的直接控制对象就是磁场电源。为了保证CSR正常运行，控制过程波形的跟踪精度、速度和稳定度，是数字电源调节器的关键所在。电源控制系统以嵌入式处理器ARM、现场可编程门阵列FPGA为核心，实现了远程数据采集、网络通讯和自动控制等功能。本系统可以进行现场监控与调试，也可以通过集成的100Mbps以太网接口电路进行远程监测与控制，CSR上各处输出电压值和电源运行状态自动传送到中央控制中心，中控中心也可以发送命令查询当前电源设备状态和各种读数。本文主要介绍了基于ARM和FPGA的嵌入式电源控制系统的设计与实现。内容主要包括：(1)系统各部分硬件电路设计与电源控制功能实现 ，硬件系统调试 。(2)装载嵌入式Linux操作系统，测试平台接口信号，通过FPGA生成多路数字PWM波形。本文目的是解决CSR电源控制系统问题，但对于许多远程数据采集与控制等问题的解决有重要参考价值

永磁伺服电动机的矢量调速控制系统研究

永磁同步伺服电动机（PMSM）以其优越的性能广泛应用于各个机械传动领域。对PMSM的研究具有非常大的实际意义和价值，尤其对于我们单位目前在建大科学工程CSR。本文采用美国TI公司专用于电动机控制的数字信号处理器（DSP）芯片TMs320LF2406A作为核心，设计和开发全数字化的PMSM矢量调速控制系统。深入研究永磁同步电动机的矢量控制理论，建立起相应数学模型，然后提出矢量控制调速方案，并通过Mat lab仿真论证其可行性。介绍了硬件，软件结构及其实现。硬件方面主要介绍了控制电路各部分的设计和调试。在硬件基础上，用T工公司DSP汇编语言编程，实现电流环和速度环的双环控制，给出了系统程序和PWM信号产生的思路，并给出了主要模块的源程序。为了提高程序的运行效率，节省存储空间和提高系统的可靠性，程序中尽可能多的采用了数据表结构。

高稳定度高压开关电源设计

本文分析了国内外开关电源的发展和现状，研究了高压开关电源的基本原理以及开关电源在电力直流操作电源系统中的应用。根据兰州重离子加速器的要求，设计了一种高稳定度高压开关电源。该系统在借鉴国外和已有的类似电源的基础上，通过采用新的元器件和新的电力电子技术设计而成。该系统以工GBT作为功率开关器件，构成BUCK开关变换器，采用脉宽调制（PWM）技术来控制输出电压的变化。系统中采用TL494、UC3637、ML57962等一系列集成电路，以实现实时采样电压反馈信号、PWM信号以及工GBT所需要的功率驱动信号。电路中采用斩波调压和逆变分开，各司其职的结构，保证了电路可靠、线性的调节；采用前馈电路进行补偿，确保系统能很好的抑制电网的中频扰动。通过MATLAB的计算仿真证明，这些措施都对对系统的性能起到了很好的作用。为了系统的安全可靠，还设计了软启动和过流保护电路。通过实验证明该系统能安全、可靠运行，达到了设计要求。

一种FPGA的嵌入式可重构机器人控制系统

提出一种基于FPGA的可重构嵌入式微处理器控制系统.在FPGA中嵌入两个NiosⅡ软核,用VHDL语言编写用户自定义组件.在一个由NiosⅡ软核组成的处理器上实现PWM信号生成、编码器信号处理以及多电机同步伺服运算等,在另一个处理器实现机器人任务管理.该控制系统针对微小型爬壁机器人的控制系统设计,不仅具有良好的实时多任务处理能力,而且具有可重构的特点,因而可应用于一类微小型机器人控制系统以提高其设计的灵活性.

螺旋桨驱动UUV推进系统研究

为了实现水下机器人(UUV,Unmanned Underwater Vehicle)的高精度控制,深入研究了螺旋桨驱动UUV推进系统各个环节运行机理,并建立了它们各自的数学模型,包括PWM模块、直流永磁电机、螺旋桨、舵的数学模型。多功能仿真试验和湖试试验的系统响应曲线基本吻合,一方面表明本文建立的推进系统模型的正确性,另一方面体现了在多功能仿真平台上调试的控制策略和控制器参数具有很大的可信度。

履带式移动机器人行动规划技术的研究

本文以８６３－５１２型号项目为背景，从运动特性、运动描述、运动控制以及运动规划等几个方面研究履带式移动机器人的行动规划技术；首先从理论上分析了履带式移动机器人的内在运动传递机理，指出了其区别于轮式移动载体的独特的运动特性，尤其是在其转向特性方面，得出了履带式移动机器人运动角速度几乎不可控原理、原地转弯转不准问题、以及履带式车辆行动规划时所要遵循的规则等重要结论，针对履带式移动机器人的纵向运动控制问题，讨论了其速度控制模型，提出了一种速度测量与控制的简单、准确、可靠的方法。在磺向运动方面，提出了一种基于ＦＭ－ＬＩＫＥ和ＡＭ－ＬＩＫＥ相结合的复合控制技术，解决了难度较大的方向控制问题。最后提供了实验结果，证明了上述方法与结论的正确性。上述方法与结论，作为８６３－５１２某型号任务的一部分，业已通过验收。

条件反射性免疫抑制及其脑机制的c-fos研究

To explore the neural mechanisms underlying conditioned immunomodulation, this study employed the classical taste aversion (CTA) behavioral paradigm to establish the conditioned humoral and cellular immunosuppression (CIS) in Wistar rats, by paring saccharin (CS) with intraperitoneal (i.p.) injection of an immunosuppressive drug cyclophophamide (UCS). C-fos immunohistochemistry method was used to observe the changes of the neuronal activities in the rat brain during the acquisition, expression and extinction of the conditioned immunosuppression (CIS). The followings are the main results: 1. Five days after one trial of CS-UCS paring, reexposure to CS alone significantly decreased the level of the anti-ovalbumin (OVA) IgG in the peripheral serum. Two trials of CS-UCS paring and three reexposures to CS not only resulted in further suppression of the primary immune response, but also reduced the numbers of peripheral lymphocytes and white blood cells. This finding indicates that CS can induce suppression of the immune function, and the magnitude of the effects is dependent on the intensity of training. 2. On day 5 following two trials of CS-UCS pairing, CS suppressed the spleen lymphocytes responsiveness to mitogens ConA, PHA and PWM, and decreased the numbers of peripheral lymphocytes and white blood cells. On day 15, only PHA induced lymphocyte proliferation was suppressed by CS. On day 30, presentation of CS did not have any effect on these immune parameters. These results suggest that the conditioned suppression of the cellular immune function can retain 5-15 days, and extinct after 30 days. 3. CTA was easily induced by one or two CS-UCS parings, and remained robust even after 30 days. These data demonstrate that CIS can be dissociated from CTA, and they may be mediated by different neural mechanisms. 4. Immunohistochemistry assays revealed a broad pattern of c-fos expression throughout the rat brain following the CS-UCS pairing and reexposure to CS, suggesting that many brain regions are involved in CIS. Some brain areas including the solitary tract nucleus (Sol), lateral parabrachial nucleus (LPB) and insular cortex (IC), showed high level c-fos expressions in response to both CS and UCS, suggesting that they may be involved in the transmission and integration of the CS and UCS signals in the brain. There were dense c-FOS positive neurons in the paraverntricular nucleus (PVN) and supraoptic nucleus (SO) of hypothalamus, subfornical organ (SFO) and area postrema (AP) etc. after two trials of CS-UCS paring and after the reexposure to CS 5 days later, but not in the first training and after the extinction of CIS (30 days later). The results reflect that these nuclei may have an important role in CIS expression, and may also response to the immunosuppression of UCS. The conditioned training and reexposure to CS 5 days later induced high level c-fos expression in the cingulate cortex (Cg), central amygdaloid nucleus (Ce), intermediate part of lateral septal nucleus (LSI) and ventrolateral parabrachial nucleus (VLPB) etc. But c-fos induction was not apparent when presenting CS 30 days later. These brain regions are mainly involved in CIS, and may be critical structures in the acquisition and expression of CIS. Some brain regions, including the frontal cortex (Fr), ventral orbital cortex (VO), IC, perirhinal cortex (PRh), LPB and the medial part of solitary nucleus (SolM), showed robust c-FOS expression following the conditioning training and reexposure to CS both on day 5 and day 30, suggesting that they are critically involved in CTA.

Systematic delay-driven power optimisation and power-driven delay optimisation of combinational circuits

With the proliferation of mobile wireless communication and embedded systems, the energy efficiency becomes a major design constraint. The dissipated energy is often referred as the product of power dissipation and the input-output delay. Most of electronic design automation techniques focus on optimising only one of these parameters either power or delay. Industry standard design flows integrate systematic methods of optimising either area or timing while for power consumption optimisation one often employs heuristics which are characteristic to a specific design. In this work we answer three questions in our quest to provide a systematic approach to joint power and delay Optimisation. The first question of our research is: How to build a design flow which incorporates academic and industry standard design flows for power optimisation? To address this question, we use a reference design flow provided by Synopsys and integrate in this flow academic tools and methodologies. The proposed design flow is used as a platform for analysing some novel algorithms and methodologies for optimisation in the context of digital circuits. The second question we answer is: Is possible to apply a systematic approach for power optimisation in the context of combinational digital circuits? The starting point is a selection of a suitable data structure which can easily incorporate information about delay, power, area and which then allows optimisation algorithms to be applied. In particular we address the implications of a systematic power optimisation methodologies and the potential degradation of other (often conflicting) parameters such as area or the delay of implementation. Finally, the third question which this thesis attempts to answer is: Is there a systematic approach for multi-objective optimisation of delay and power? A delay-driven power and power-driven delay optimisation is proposed in order to have balanced delay and power values. This implies that each power optimisation step is not only constrained by the decrease in power but also the increase in delay. Similarly, each delay optimisation step is not only governed with the decrease in delay but also the increase in power. The goal is to obtain multi-objective optimisation of digital circuits where the two conflicting objectives are power and delay. The logic synthesis and optimisation methodology is based on AND-Inverter Graphs (AIGs) which represent the functionality of the circuit. The switching activities and arrival times of circuit nodes are annotated onto an AND-Inverter Graph under the zero and a non-zero-delay model. We introduce then several reordering rules which are applied on the AIG nodes to minimise switching power or longest path delay of the circuit at the pre-technology mapping level. The academic Electronic Design Automation (EDA) tool ABC is used for the manipulation of AND-Inverter Graphs. We have implemented various combinatorial optimisation algorithms often used in Electronic Design Automation such as Simulated Annealing and Uniform Cost Search Algorithm. Simulated Annealing (SMA) is a probabilistic meta heuristic for the global optimization problem of locating a good approximation to the global optimum of a given function in a large search space. We used SMA to probabilistically decide between moving from one optimised solution to another such that the dynamic power is optimised under given delay constraints and the delay is optimised under given power constraints. A good approximation to the global optimum solution of energy constraint is obtained. Uniform Cost Search (UCS) is a tree search algorithm used for traversing or searching a weighted tree, tree structure, or graph. We have used Uniform Cost Search Algorithm to search within the AIG network, a specific AIG node order for the reordering rules application. After the reordering rules application, the AIG network is mapped to an AIG netlist using specific library cells. Our approach combines network re-structuring, AIG nodes reordering, dynamic power and longest path delay estimation and optimisation and finally technology mapping to an AIG netlist. A set of MCNC Benchmark circuits and large combinational circuits up to 100,000 gates have been used to validate our methodology. Comparisons for power and delay optimisation are made with the best synthesis scripts used in ABC. Reduction of 23% in power and 15% in delay with minimal overhead is achieved, compared to the best known ABC results. Also, our approach is also implemented on a number of processors with combinational and sequential components and significant savings are achieved.