The effects of J-gate potential and interfaces on donor exchange coupling in the Kane quantum computer architecture

We calculate the electron exchange coupling for a phosphorus donor pair in silicon perturbed by a J-gate potential and the boundary effects of the silicon host geometry. In addition to the electron-electron exchange interaction we also calculate the contact hyperfine interaction between the donor nucleus and electron as a function of the varying experimental conditions. Donor separation, depth of the P nuclei below the silicon oxide layer and J-gate voltage become decisive factors in determining the strength of both the exchange coupling and hyperfine interaction-both crucial components for qubit operations in the Kane quantum computer. These calculations were performed using an anisotropic effective-mass Hamiltonian approach. The behaviour of the donor exchange coupling as a function of the parameters varied in this work provides relevant information for the experimental design of these devices.

Quantum-gate characterization in an extended Hilbert space

We describe an approach for characterizing the process performed by a quantum gate using quantum process tomography, by first modeling the gate in an extended Hilbert space, which includes nonqubit degrees of freedom. To prevent unphysical processes from being predicted, present quantum process tomography procedures incorporate mathematical constraints, which make no assumptions as to the actual physical nature of the system being described. By contrast, the procedure presented here assumes a particular class of physical processes, and enforces physicality by fitting the data to this model. This allows quantum process tomography to be performed using a smaller experimental data set, and produces parameters with a direct physical interpretation. The approach is demonstrated by example of mode matching in an all-optical controlled-NOT gate. The techniques described are general and could be applied to other optical circuits or quantum computing architectures.

Demonstration of a simple entangling optical gate and its use in bell-state analysis

We demonstrate a new architecture for an optical entangling gate that is significantly simpler than previous realizations, using partially polarizing beam splitters so that only a single optical mode-matching condition is required. We demonstrate operation of a controlled-z gate in both continuous-wave and pulsed regimes of operation, fully characterizing it in each case using quantum process tomography. We also demonstrate a fully resolving, nondeterministic optical Bell-state analyzer based on this controlled-z gate. This new architecture is ideally suited to guided optics implementations of optical gates.

Quantum gate based on Stark tunable nanocrystal interactions with ultrahigh-Q/V field modes in fused silica microcavities

We investigate the use of nanocrystal quantum dots as a quantum bus element for preparing various quantum resources for use in photonic quantum technologies. Using the Stark-tuning property of nanocrystal quantum dots as well as the biexciton transition, we demonstrate a photonic controlled-NOT (CNOT) interaction between two logical photonic qubits comprising two cavity field modes each. We find the CNOT interaction to be a robust generator of photonic Bell states, even with relatively large biexciton losses. These results are discussed in light of the current state of the art of both microcavity fabrication and recent advances in nanocrystal quantum dot technology. Overall, we find that such a scheme should be feasible in the near future with appropriate refinements to both nanocrystal fabrication technology and microcavity design. Such a gate could serve as an active element in photonic-based quantum technologies.

Side boundary gate, Lahz House, Spring Hill

House beyond with skylight to bathroom visible on left. Winner of the Robin Dods Award RAIA Queensland Chapter 1990

Performance characterisation of 42.65 Gbit/s dual-gate asynchronous digital optical regenerator using single MZM

The tolerance of a 42.65 Gbit/s dual-gate asynchronous digital optical regenerator using a single Mach-Zehnder modulator to optical signal-to-noise-ratio degradation and chromatic dispersion is experimentally demonstrated.

Study of "chopper/inverter" AC drives using gate turn-off thyristors"

DUE TO COPYRIGHT RESTRICTIONS ONLY AVAILABLE FOR CONSULTATION AT ASTON UNIVERSITY LIBRARY AND INFORMATION SERVICES WITH PRIOR ARRANGEMENT

Species differential regulation of COX2 can be described by an NFκB-dependent logic AND gate

Cyclooxygenase 2 (COX2), a key regulatory enzyme of the prostaglandin/eicosanoid pathway, is an important target for anti-inflammatory therapy. It is highly induced by pro-inflammatory cytokines in a Nuclear factor kappa B (NFκB)-dependent manner. However, the mechanisms determining the amplitude and dynamics of this important pro-inflammatory event are poorly understood. Furthermore, there is significant difference between human and mouse COX2 expression in response to the inflammatory stimulus tumor necrosis factor alpha (TNFα). Here, we report the presence of a molecular logic AND gate composed of two NFκB response elements (NREs) which controls the expression of human COX2 in a switch-like manner. Combining quantitative kinetic modeling and thermostatistical analysis followed by experimental validation in iterative cycles, we show that the human COX2 expression machinery regulated by NFκB displays features of a logic AND gate. We propose that this provides a digital, noise-filtering mechanism for a tighter control of expression in response to TNFα, such that a threshold level of NFκB activation is required before the promoter becomes active and initiates transcription. This NFκB-regulated AND gate is absent in the mouse COX2 promoter, most likely contributing to its differential graded response in promoter activity and protein expression to TNFα. Our data suggest that the NFκB-regulated AND gate acts as a novel mechanism for controlling the expression of human COX2 to TNFα, and its absence in the mouse COX2 provides the foundation for further studies on understanding species-specific differential gene regulation.

Field programmable gate array based target detection and gesture recognition

The move from Standard Definition (SD) to High Definition (HD) represents a six times increases in data, which needs to be processed. With expanding resolutions and evolving compression, there is a need for high performance with flexible architectures to allow for quick upgrade ability. The technology advances in image display resolutions, advanced compression techniques, and video intelligence. Software implementation of these systems can attain accuracy with tradeoffs among processing performance (to achieve specified frame rates, working on large image data sets), power and cost constraints. There is a need for new architectures to be in pace with the fast innovations in video and imaging. It contains dedicated hardware implementation of the pixel and frame rate processes on Field Programmable Gate Array (FPGA) to achieve the real-time performance. ^ The following outlines the contributions of the dissertation. (1) We develop a target detection system by applying a novel running average mean threshold (RAMT) approach to globalize the threshold required for background subtraction. This approach adapts the threshold automatically to different environments (indoor and outdoor) and different targets (humans and vehicles). For low power consumption and better performance, we design the complete system on FPGA. (2) We introduce a safe distance factor and develop an algorithm for occlusion occurrence detection during target tracking. A novel mean-threshold is calculated by motion-position analysis. (3) A new strategy for gesture recognition is developed using Combinational Neural Networks (CNN) based on a tree structure. Analysis of the method is done on American Sign Language (ASL) gestures. We introduce novel point of interests approach to reduce the feature vector size and gradient threshold approach for accurate classification. (4) We design a gesture recognition system using a hardware/ software co-simulation neural network for high speed and low memory storage requirements provided by the FPGA. We develop an innovative maximum distant algorithm which uses only 0.39% of the image as the feature vector to train and test the system design. Database set gestures involved in different applications may vary. Therefore, it is highly essential to keep the feature vector as low as possible while maintaining the same accuracy and performance^

Thermal stability study of AlGaN/GaN MOS-HEMTs using Gd2O3 as gate dielectric

Thermal stability of AlGaN/GaN MOS-HEMTs and -diodes using Gd_(2)O_(3) are investigated by means of different thermal cycles and storage tests up to 500ºC for one week. IV DC and pulsed characteristics of the devices before and after the processes are evaluated and compared with conventional HEMTs. Results show that the devices with Gd_(2)O_(3) dielectric layer have lower leakage current and a more stable behavior during thermal treatment processes compared with conventional devices. In fact, an excellent on/off ratio of about 108 and a stable V_(t) is observed after storage at high temperature. The beneficial effects of Gd_(2)O_(3) on trapping effects of MOS-HEMTs are also dis-cussed.

Microwave Plasma Assisted ALD Development for the Deposition of Gate Oxides & ALD of High-k Dielectrics

The semiconductor industry's urge towards faster, smaller and cheaper integrated circuits has lead the industry to smaller node devices. The integrated circuits that are now under volume production belong to 22 nm and 14 nm technology nodes. In 2007 the 45 nm technology came with the revolutionary high- /metal gate structure. 22 nm technology utilizes fully depleted tri-gate transistor structure. The 14 nm technology is a continuation of the 22 nm technology. Intel is using second generation tri-gate technology in 14 nm devices. After 14 nm, the semiconductor industry is expected to continue the scaling with 10 nm devices followed by 7 nm. Recently, IBM has announced successful production of 7 nm node test chips. This is the fashion how nanoelectronics industry is proceeding with its scaling trend. For the present node of technologies selective deposition and selective removal of the materials are required. Atomic layer deposition and the atomic layer etching are the respective techniques used for selective deposition and selective removal. Atomic layer deposition still remains as a futuristic manufacturing approach that deposits materials and lms in exact places. In addition to the nano/microelectronics industry, ALD is also widening its application areas and acceptance. The usage of ALD equipments in industry exhibits a diversi cation trend. With this trend, large area, batch processing, particle ALD and plasma enhanced like ALD equipments are becoming prominent in industrial applications. In this work, the development of an atomic layer deposition tool with microwave plasma capability is described, which is a ordable even for lightly funded research labs.

Pearly gate of the true life and doctrine for believers in Christ. ...

"The following is my understanding of scripture teaching in harmony with shaker principles and practice. A.G. Hollister."--Pref.