Geração automática de hardware a partir de especificações formais: estendendo uma abordagem de tradução

Removing inconsistencies in a project is a less expensive activity when done in the early steps of design. The use of formal methods improves the understanding of systems. They have various techniques such as formal specification and verification to identify these problems in the initial stages of a project. However, the transformation from a formal specification into a programming language is a non-trivial task and error prone, specially when done manually. The aid of tools at this stage can bring great benefits to the final product to be developed. This paper proposes the extension of a tool whose focus is the automatic translation of specifications written in CSPM into Handel-C. CSP is a formal description language suitable for concurrent systems, and CSPM is the notation used in tools support. Handel-C is a programming language whose result can be compiled directly into FPGA s. Our extension increases the number of CSPM operators accepted by the tool, allowing the user to define local processes, to rename channels in a process and to use Boolean guards on external choices. In addition, we also propose the implementation of a communication protocol that eliminates some restrictions on parallel composition of processes in the translation into Handel-C, allowing communication in a same channel between multiple processes to be mapped in a consistent manner and that improper communication in a channel does not ocurr in the generated code, ie, communications that are not allowed in the system specification

Projeto e implementação em FPGA de um processador com conjunto de instrução reconfigurável utilizando VHDL

The Reconfigurable Computing is an intermediate solution at the resolution of complex problems, making possible to combine the speed of the hardware with the flexibility of the software. An reconfigurable architecture possess some goals, among these the increase of performance. The use of reconfigurable architectures to increase the performance of systems is a well known technology, specially because of the possibility of implementing certain slow algorithms in the current processors directly in hardware. Amongst the various segments that use reconfigurable architectures the reconfigurable processors deserve a special mention. These processors combine the functions of a microprocessor with a reconfigurable logic and can be adapted after the development process. Reconfigurable Instruction Set Processors (RISP) are a subgroup of the reconfigurable processors, that have as goal the reconfiguration of the instruction set of the processor, involving issues such formats, operands and operations of the instructions. This work possess as main objective the development of a RISP processor, combining the techniques of configuration of the set of executed instructions of the processor during the development, and reconfiguration of itself in execution time. The project and implementation in VHDL of this RISP processor has as intention to prove the applicability and the efficiency of two concepts: to use more than one set of fixed instructions, with only one set active in a given time, and the possibility to create and combine new instructions, in a way that the processor pass to recognize and use them in real time as if these existed in the fixed set of instruction. The creation and combination of instructions is made through a reconfiguration unit, incorporated to the processor. This unit allows the user to send custom instructions to the processor, so that later he can use them as if they were fixed instructions of the processor. In this work can also be found simulations of applications involving fixed and custom instructions and results of the comparisons between these applications in relation to the consumption of power and the time of execution, which confirm the attainment of the goals for which the processor was developed

Utilizando programação orientada a aspectos no projeto de sistemas hardware desenvolvidos com SystemC

New programming language paradigms have commonly been tested and eventually incorporated into hardware description languages. Recently, aspect-oriented programming (AOP) has shown successful in improving the modularity of object-oriented and structured languages such Java, C++ and C. Thus, one can expect that, using AOP, one can improve the understanding of the hardware systems under design, as well as make its components more reusable and easier to maintain. We apply AOP in applications developed using the SystemC library. Several examples will be presented illustrating how to combine AOP and SystemC. During the presentation of these examples, the benefits of this new approach will also be discussed

Arquitetura hardware/software de um núcleo NCAP segundo o padrão IEEE 1451.1: uma prova de conceito

Os sensores inteligentes são dispositivos que se diferenciam dos sensores comuns por apresentar capacidade de processamento sobre os dados monitorados. Eles tipicamente são compostos por uma fonte de alimentação, transdutores (sensores e atuadores), memória, processador e transceptor. De acordo com o padrão IEEE 1451 um sensor inteligente pode ser dividido em módulos TIM e NCAP que devem se comunicar através de uma interface padronizada chamada TII. O módulo NCAP é a parte do sensor inteligente que comporta o processador. Portanto, ele é o responsável por atribuir a característica de inteligência ao sensor. Existem várias abordagens que podem ser utilizadas para o desenvolvimento desse módulo, dentre elas se destacam aquelas que utilizam microcontroladores de baixo custo e/ou FPGA. Este trabalho aborda o desenvolvimento de uma arquitetura hardware/software para um módulo NCAP segundo o padrão IEEE 1451.1. A infra-estrutura de hardware é composta por um driver de interface RS-232, uma memória RAM de 512kB, uma interface TII, o processador embarcado NIOS II e um simulador do módulo TIM. Para integração dos componentes de hardware é utilizada ferramenta de integração automática SOPC Builder. A infra-estrutura de software é composta pelo padrão IEEE 1451.1 e pela aplicação especí ca do NCAP que simula o monitoramento de pressão e temperatura em poços de petróleo com o objetivo de detectar vazamento. O módulo proposto é embarcado em uma FPGA e para a sua prototipação é usada a placa DE2 da Altera que contém a FPGA Cyclone II EP2C35F672C6. O processador embarcado NIOS II é utilizado para dar suporte à infra-estrutura de software do NCAP que é desenvolvido na linguagem C e se baseia no padrão IEEE 1451.1. A descrição do comportamento da infra-estrutura de hardware é feita utilizando a linguagem VHDL

MATHEMATICA notebook for computing tetrahedral finite element shape functions and matrices for the Helmholtz equation

A MATHEMATICA notebook to compute the elements of the matrices which arise in the solution of the Helmholtz equation by the finite element method (nodal approximation) for tetrahedral elements of any approximation order is presented. The results of the notebook enable a fast computational implementation of finite element codes for high order simplex 3D elements reducing the overheads due to implementation and test of the complex mathematical expressions obtained from the analytical integrations. These matrices can be used in a large number of applications related to physical phenomena described by the Poisson, Laplace and Schrodinger equations with anisotropic physical properties.

Arquitetura multiprocessada e reconfigurável para a síntese de redes de Petri em hardware

Uma arquitetura reconfigurável e multiprocessada para a implementação física de Redes de Petri foi desenvolvida em VHDL e mapeada sobre um FPGA. Convencionalmente, as Redes de Petri são transformadas em uma linguagem de descrição de hardware no nível de transferências entre registradores e um processo de síntese de alto nível é utilizado para gerar as funções booleanas e tabelas de transição de estado para que se possa, finalmente, mapeá-las num FPGA (Morris et al., 2000) (Soto and Pereira, 2001). A arquitetura proposta possui blocos lógicos reconfiguráveis desenvolvidos exclusivamente para a implementação dos lugares e das transições da rede, não sendo necessária a descrição da rede em níveis de abstração intermediários e nem a utilização de um processo de síntese para realizar o mapeamento da rede na arquitetura. A arquitetura permite o mapeamento de modelos de Redes de Petri com diferenciação entre as marcas e associação de tempo no disparo das transições, sendo composta por um arranjo de processadores reconfiguráveis, cada um dos quais representando o comportamento de uma transição da Rede de Petri a ser mapeada e por um sistema de comunicação, implementado por um conjunto de roteadores que são capazes de enviar pacotes de dados de um processador reconfigurável a outro. A arquitetura proposta foi validada num FPGA de 10.570 elementos lógicos com uma topologia que permitiu a implementação de Redes de Petri de até 9 transições e 36 lugares, atingindo uma latência de 15,4ns e uma vazão de até 17,12GB/s com uma freqüência de operação de 64,58MHz.

Interpolating EFGM for computing continuous and discontinuous electromagnetic fields

Purpose - This paper proposes an interpolating approach of the element-free Galerkin method (EFGM) coupled with a modified truncation scheme for solving Poisson's boundary value problems in domains involving material non-homogeneities. The suitability and efficiency of the proposed implementation are evaluated for a given set of test cases of electrostatic field in domains involving different material interfaces.Design/methodology/approach - the authors combined an interpolating approximation with a modified domain truncation scheme, which avoids additional techniques for enforcing the Dirichlet boundary conditions and for dealing with material interfaces usually employed in meshfree formulations.Findings - the local electric potential and field distributions were correctly described as well as the global quantities like the total potency and resistance. Since, the treatment of the material interfaces becomes practically the same for both the finite element method (FEM) and the proposed EFGM, FEM-oriented programs can, thus, be easily extended to provide EFGM approximations.Research limitations/implications - the robustness of the proposed formulation became evident from the error analyses of the local and global variables, including in the case of high-material discontinuity.Practical implications - the proposed approach has shown to be as robust as linear FEM. Thus, it becomes an attractive alternative, also because it avoids the use of additional techniques to deal with boundary/interface conditions commonly employed in meshfree formulations.Originality/value - This paper reintroduces the domain truncation in the EFGM context, but by using a set of interpolating shape functions the authors avoided the use of Lagrange multipliers as well Mathematics in Engineering high-material discontinuity.

A simple prescription for computing the stress-energy tensor

A non-variational technique for computing the stress-energy tensor is presented. The prescription is used, among other things, to obtain the correct field equations for Prasanna's highly nonlinear electrodynamics.

On computing discriminants of subfields of Q(zeta(pr))

The conductor-discriminant formula, namely, the Hasse Theorem, states that if a number field K is fixed by a subgroup H of Gal(Q(zeta(n))/Q), the discriminant of K can be obtained from H by computing the product of the conductors of all characters defined modulo n which are associated to K. By calculating these conductors explicitly, we derive a formula to compute the discriminant of any subfield of Q(zeta(p)r), where p is an odd prime and r is a positive integer. (C) 2002 Elsevier B.V. (USA).

On the dissimilarity between the algorithms for computing the symmetric energy-momentum tensor in ordinary field theory and general relativity

The recipe used to compute the symmetric energy-momentum tensor in the framework of ordinary field theory bears little resemblance to that used in the context of general relativity, if any. We show that if one stal ts fi om the field equations instead of the Lagrangian density, one obtains a unified algorithm for computing the symmetric energy-momentum tensor in the sense that it can be used for both usual field theory and general relativity.

Analog Modeling of Human Cognitive Functions with Tripartite Synapses

Searching for an understanding of how the brain supports conscious processes, cognitive scientists have proposed two main classes of theory: Global Workspace and Information Integration theories. These theories seem to be complementary, but both still lack grounding in terms of brain mechanisms responsible for the production of coherent and unitary conscious states. Here we propose following James Robertson's "Astrocentric Hypothesis" - that conscious processing is based on analog computing in astrocytes. The "hardware" for these computations is calcium waves mediated by adenosine triphosphate signaling. Besides presenting our version of this hypothesis, we also review recent findings on astrocyte morphology that lend support to their functioning as Local Hubs (composed of protoplasmic astrocytes) that integrate synaptic activity, and as a Master Hub (composed, in the human brain, by a combination of interlaminar, fibrous, polarized and varicose projection astrocytes) that integrates whole-brain activity.

Algorithm for computing the propagator for higher derivative gravity theories

A simple algorithm for computing the propagator for higher derivative gravity theories based on the Barnes-Rivers operators is presented. The prescription is used, among other things, to obtain the propagator for quadratic gravity in an unconventional gauge. We also find the propagator for both gravity and quadratic gravity in an interesting gauge recently baptized the Einstein gauge [Hitzer and Dehnen, Int. J. Theor. Phys. 36 (1997), 559].

N-methyl-D-aspartate channel and consciousness: From signal coincidence detection to quantum computing

Research on Blindsight, Neglect/Extinction and Phantom limb syndromes, as well as electrical measurements of mammalian brain activity, have suggested the dependence of vivid perception on both incoming sensory information at primary sensory cortex and reentrant information from associative cortex. Coherence between incoming and reentrant signals seems to be a necessary condition for (conscious) perception. General reticular activating system and local electrical synchronization are some of the tools used by the brain to establish coarse coherence at the sensory cortex, upon which biochemical processes are coordinated. Besides electrical synchrony and chemical modulation at the synapse, a central mechanism supporting such a coherence is the N-methyl-D-aspartate channel, working as a 'coincidence detector' for an incoming signal causing the depolarization necessary to remove Mg 2+, and reentrant information releasing the glutamate that finally prompts Ca 2+ entry. We propose that a signal transduction pathway activated by Ca 2+ entry into cortical neurons is in charge of triggering a quantum computational process that accelerates inter-neuronal communication, thus solving systemic conflict and supporting the unity of consciousness. © 2001 Elsevier Science Ltd.

On computing discriminants of subfields of ℚ (ζp r)

The conductor-discriminant formula, namely, the Hasse Theorem, states that if a number field K is fixed by a subgroup H of Gal(ℚ(ζn)/ℚ), the discriminant of K can be obtained from H by computing the product of the conductors of all characters defined modulo n which are associated to K. By calculating these conductors explicitly, we derive a formula to compute the discriminant of any subfield of ℚ(ζpr), where p is an odd rime and r is a positive integer. © 2002 Elsevier Science USA.

Evolvable hardware applied to voice recognition

This paper presents some results of the application on Evolvable Hardware (EHW) in the area of voice recognition. Evolvable Hardware is able to change inner connections, using genetic learning techniques, adapting its own functionality to external condition changing. This technique became feasible by the improvement of the Programmable Logic Devices. Nowadays, it is possible to have, in a single device, the ability to change, on-line and in real-time, part of its own circuit. This work proposes a reconfigurable architecture of a system that is able to receive voice commands to execute special tasks as, to help handicapped persons in their daily home routines. The idea is to collect several voice samples, process them through algorithms based on Mel - Ceptrais theory to obtain their numerical coefficients for each sample, which, compose the universe of search used by genetic algorithm. The voice patterns considered, are limited to seven sustained Portuguese vowel phonemes (a, eh, e, i, oh, o, u).