Controle digital através de dispositivo FPGA aplicado a um retificador trifásico híbrido operando com modulação por histerese variável

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

Filtragem digital e reconstrução de sinais em frequência intermediária usando FPGA

O presente trabalho trata da filtragem e reconstrução de sinais em frequência intermediária usando FPGA. É feito o desenvolvimento de algoritmos usando processamento digital de sinais e também a implementação dos mesmos, constando desde o projeto da placa de circuito impresso, montagem e teste. O texto apresenta um breve estudo de amostragem e reconstrução de sinais em geral. Especial atenção é dada à amostragem de sinais banda-passante e à análise de questões práticas de reconstrução de sinais em frequência intermediária. Dois sistemas de reconstrução de sinais baseados em processamento digital de sinais, mais especificamente reamostragem no domínio discreto, são apresentados e analisados. São também descritas teorias de processos de montagem e soldagem de placas eletrônicas com objetivo de definir uma metodologia de projeto, montagem e soldagem de placas eletrônicas. Tal metodologia é aplicada no projeto e manufatura do protótipo de um módulo de filtragem digital para repetidores de telefonia celular. O projeto, implementado usando FPGA, é baseado nos dois sistemas supracitados. Ao final do texto, resultados obtidos em experimentos de filtragem digital e reconstrução de sinais em frequência intermediária com o protótipo desenvolvido são apresentados.

Desenvolvimento de um sistema de instrumentação de medição de vibração mecânica em máquina rotativas, em tempo real, embarcado em FPGA

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

Phenomenological Interpretation of Impedance/Capacitance Measurements on Organic Electronic Devices Under Illumination

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

SeP hole injection layer for devices based on organic materials

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

Disorder induced interface states and their influence on the AI/Ge nanowires Schottky devices

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

Development of a CAD system for automatic classification of microcalcifications based on FPGA

This paper presents a Computer Aided Diagnosis (CAD) system that automatically classifies microcalcifications detected on digital mammograms into one of the five types proposed by Michele Le Gal, a classification scheme that allows radiologists to determine whether a breast tumor is malignant or not without the need for surgeries. The developed system uses a combination of wavelets and Artificial Neural Networks (ANN) and is executed on an Altera DE2-115 Development Kit, a kit containing a Field-Programmable Gate Array (FPGA) that allows the system to be smaller, cheaper and more energy efficient. Results have shown that the system was able to correctly classify 96.67% of test samples, which can be used as a second opinion by radiologists in breast cancer early diagnosis. (C) 2013 The Authors. Published by Elsevier B.V.

Sprayed films of europium complexes toward light conversion devices

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

Investigation of Bulk and DTMOS triple-gate devices under 60 MeV proton irradiation

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

Investigations on PVP/Y3BO6:Eu3+, a red Luminescent composite for lighting devices based on near UV-LEDs

This work deals with a red phosphor. Y3BO6:Eu3+, and its corresponding poly(N-vinylpyrrolidone) (PVP)/Y3BO6:Eu3+ luminescent composite film suitable for applications in the next generation of Hg-free lamps based on near ultraviolet (UV) light emitting diodes (LEDs). Well crystallized samples of Y3BO6 powders with the Eu3+ content up to 20 mol% were prepared by the Pechini method. After structural, morphological and optical characterization, the best doping rate of Eu3+ in the matrix was determined to be 15 mol%. This optimal powder, which is highly friable, was easily ground into fine particles and homogeneously dispersed into a PVP polymer solution to give rise to a polymer phosphor composite. Structural and optical features of the composite film have been studied and compared to those of a pristine PVP film and Y3BO6:Eu3+ powder. All the characterization (XRD, SAXS, luminescence...) proved that the red phosphor particles are well incorporated into the polymer composite film which exhibited the characteristic red emission of Eu3+ under UV light excitation. Furthermore, photostability of the polymer/phosphor composite film under UV-LED irradiation was evaluated from exposure to accelerated artificial photoageing at wavelengths above 300 nm.

Reconhecimento de voz para aplicações em automação implementado em FPGA

In many movies of scientific fiction, machines were capable of speaking with humans. However mankind is still far away of getting those types of machines, like the famous character C3PO of Star Wars. During the last six decades the automatic speech recognition systems have been the target of many studies. Throughout these years many technics were developed to be used in applications of both software and hardware. There are many types of automatic speech recognition system, among which the one used in this work were the isolated word and independent of the speaker system, using Hidden Markov Models as the recognition system. The goals of this work is to project and synthesize the first two steps of the speech recognition system, the steps are: the speech signal acquisition and the pre-processing of the signal. Both steps were developed in a reprogrammable component named FPGA, using the VHDL hardware description language, owing to the high performance of this component and the flexibility of the language. In this work it is presented all the theory of digital signal processing, as Fast Fourier Transforms and digital filters and also all the theory of speech recognition using Hidden Markov Models and LPC processor. It is also presented all the results obtained for each one of the blocks synthesized e verified in hardware

Bit-parallel coprocessor for standard ECC-GF(2m) on FPGA

This paper presents the design of a high-speed coprocessor for Elliptic Curve Cryptography over binary Galois Field (ECC- GF(2m)). The purpose of our coprocessor is to accelerate the scalar multiplication performed over elliptic curve points represented by affine coordinates in polynomial basis. Our method consists of using elliptic curve parameters over GF(2163) in accordance with international security requirements to implement a bit-parallel coprocessor on field-programmable gate-array (FPGA). Our coprocessor performs modular inversion by using a process based on the Stein's algorithm. Results are presented and compared to results of other related works. We conclude that our coprocessor is suitable for comparing with any other ECC-hardware proposal, since its speed is comparable to projective coordinate designs.