Desenvolvimento de uma arquitetura em hardware prototipada em FPGA para aplicações genéricas utilizando redes neurais artificiais embarcadas

This work proposes hardware architecture, VHDL described, developed to embedded Artificial Neural Network (ANN), Multilayer Perceptron (MLP). The present work idealizes that, in this architecture, ANN applications could easily embed several different topologies of MLP network industrial field. The MLP topology in which the architecture can be configured is defined by a simple and specifically data input (instructions) that determines the layers and Perceptron quantity of the network. In order to set several MLP topologies, many components (datapath) and a controller were developed to execute these instructions. Thus, an user defines a group of previously known instructions which determine ANN characteristics. The system will guarantee the MLP execution through the neural processors (Perceptrons), the components of datapath and the controller that were developed. In other way, the biases and the weights must be static, the ANN that will be embedded must had been trained previously, in off-line way. The knowledge of system internal characteristics and the VHDL language by the user are not needed. The reconfigurable FPGA device was used to implement, simulate and test all the system, allowing application in several real daily problems

Implementação de processador banda base ofdma para downlink lte em fpga

This work treats of an implementation OFDMA baseband processor in hardware for LTE Downlink. The LTE or Long Term Evolution consist the last stage of development of the technology called 3G (Mobile System Third Generation) which offers an increasing in data rate and more efficiency and flexibility in transmission with application of advanced antennas and multiple carriers techniques. This technology applies in your physical layer the OFDMA technical (Orthogonal Frequency Division Multiple Access) for generation of signals and mapping of physical resources in downlink and has as base theoretical to OFDM multiple carriers technique (Orthogonal Frequency Division Multiplexing). With recent completion of LTE specifications, different hardware solutions have been developed, mainly, to the level symbol processing where the implementation of OFDMA processor in base band is commonly considered, because it is also considered a basic architecture of others important applications. For implementation of processor, the reconfigurable hardware offered by devices as FPGA are considered which shares not only to meet the high requirements of flexibility and adaptability of LTE as well as offers possibility of an implementation quick and efficient. The implementation of processor in reconfigurable hardware meets the specifications of LTE physical layer as well as have the flexibility necessary for to meet others standards and application which use OFDMA processor as basic architecture for your systems. The results obtained through of simulation and verification functional system approval the functionality and flexibility of processor implemented

Projeto em FPGA de um controlador unificado para correção de fator de potência em retificadores boost bidirecionais monofásicos

The use of Field Programmable Gate Array (FPGA) for development of digital control strategies for power electronics applications has aroused a growing interest of many researchers. This interest is due to the great advantages offered by FPGA, which include: lower design effort, high performance and highly flexible prototyping. This work proposes the development and implementation of an unified one-cycle controller for boost CFP rectifier based on FPGA. This controller can be applied to a total of twelve converters, six inverters and six rectifiers defined by four single phase VSI topologies and three voltage modulation types. The topologies considered in this work are: full-bridge, interleaved full-bridge, half-bridge and interleaved half-bridge. While modulations are classified in bipolar voltage modulation (BVM), unipolar voltage modulation (UVM) and clamped voltage modulation (CVM). The proposed project is developed and prototyped using tools Matlab/Simulink® together with the DSP Builder library provided by Altera®. The proposed controller was validated with simulation and experimental results

Bifurcation Analysis of a Van der Pol-Duffing Circuit with Parallel Resistor

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Design and Analysis of Optical Interconnection Networks for a Dataflow Parallel Computer

This work shows the design, simulation, and analysis of two optical interconnection networks for a Dataflow parallel computer architecture. To verify the optical interconnection network performance on the Dataflow architecture, we have analyzed the load balancing among the processors during the parallel programs executions. The load balancing is a very important parameter because it is directly associated to the dataflow parallelism degree. This article proves that optical interconnection networks designed with simple optical devices can provide efficiently the dataflow requirements of a high performance communication system.

An investigation on parallel, divergent and convergent acetylene dual jet diffusion flames

Results are presented and discussed of an experimental investigation on acetylene turbulent dual jet diffusion flames. The study includes parameters of flames in parallel, divergent and convergent configurations. Tests with two parallel jets with addition of helium in the fuel stream were also performed and analysed. The variation of overall flame length and of other name physical characteristics, such as width, volume and conditions for lifting, are presented as functions of burner tip Reynolds number, jet distance from each other and inclination angle. The effects of diluent concentration in the fuel gas stream are presented for single and two parallel jets. (C) 1999 Elsevier B.V. Ltd.

A 2kW interleaved ZCS-FM boost rectifier digitally controlled by FPGA device

This paper presents a 2kW single-phase high power factor boost rectifier with four cells in interleave connection, operating in critical conduction mode, and employing a soft-switching technique, controlled by Field Programmable Gate Array (FPGA). The soft-switching technique Is based on zero-current-switching (ZCS) cells, providing ZC (zero-current) turn-on and ZCZV (zero-current-zero-voltage) turn-off for the active switches, and ZV (zero-voltage) turn-on and ZC (zero-current) turn-off for the boost diodes. The disadvantages related 'to reverse recovery effects of boost diodes operated in continuous conduction mode (additional losses, and electromagnetic interference (EMI) problems) are minimized, due to the operation in critical conduction mode. In addition, due to the Interleaving technique, the rectifer's features include the reduction in the input current ripple, the reduction in the output voltage ripple, the use of low stress devices, low volume for the EMI input filter, high input power factor (PF), and low total harmonic distortion (THD) In the input current, in compliance with the TEC61000-3-2 standards. The digital controller has been developed using a hardware description language (VHDL) and implemented using a XC2S200E-SpartanII-E/Xilinx FPGA device, performing a true critical conduction operation mode for four interleaved cells, and a closed-loop to provide the output voltage regulation, like as a pre-regulator rectifier. Experimental results are presented for a 2kW implemented prototype with four interleaved cells, 400V nominal output voltage and 220V(rms) nominal input voltage, in order to verify the feasibility and performance of the proposed digital control through the use of a FPGA device.

A VHDL-based protocol controller for NCAP processors

This work presents the development of an IEEE 1451.2 protocol controller based on a low-cost FPGA that is directly connected to the parallel port of a conventional personal computer. In this manner it is possible to implement a Network Capable Application Processor (NCAP) based on a personal computer, without parallel port modifications. This approach allows supporting the ten signal lines of the 10-wire IEEE 1451.2 Transducer Independent Interface (TII), that connects the network processor to the Smart Transducer Interface Module (STIM) also defined in the IEEE 1451.2 standard. The protocol controller is connected to the STIM through the TII's physical interface, enabling the portability of the application at the transducer and network processor level. The protocol controller architecture was fully developed in VHDL language and we have projected a special prototype configured in a general-purpose programmable logic device. We have implemented two versions of the protocol controller, which is based on IEEE 1451 standard, and we have obtained results using simulation and experimental tests. (c) 2008 Elsevier B.V. All rights reserved.

Differential-Evolution-Based Optimization of the Dynamic Response for Parallel Operation of Inverters With No Controller Interconnection

In this paper, the use of differential evolution ( DE), a global search technique inspired by evolutionary theory, to find the parameters that are required to achieve optimum dynamic response of parallel operation of inverters with no interconnection among the controllers is proposed. Basically, in order to reach such a goal, the system is modeled in a certain way that the slopes of P-omega and Q-V curves are the parameters to be tuned. Such parameters, when properly tuned, result in system's eigenvalues located in positions that assure the system's stability and oscillation-free dynamic response with minimum settling time. This paper describes the modeling approach and provides an overview of the motivation for the optimization and a description of the DE technique. Simulation and experimental results are also presented, and they show the viability of the proposed method.

On the dynamic behaviour of a mass supported by a parallel combination of a spring and an elastically connected damper

This paper presents a consistent and concise analysis of the free and forced vibration of a mass supported by a parallel combination of a spring and an elastically supported damper (a Zener model). The results are presented in a compact form and the physical behaviour of the system is emphasised. This system is very similar to the conventional single-degree-of freedom system (sdof)-(Voigt model), but the dynamics can be quite different depending on the system parameters. The usefulness of the additional spring in series with the damper is investigated, and optimum damping values for the system subject to different types of excitation are determined and compared.There are three roots to the characteristic equation for the Zener model; two are complex conjugates and the third is purely real. It is shown that it is not possible to achieve critical damping of the complex roots unless the additional stiffness is at least eight times that of the main spring. For a harmonically excited system, there are some possible advantages in using the additional spring when the transmitted force to the base is of interest, but when the displacement response of the system is of interest then the benefits are marginal. It is shown that the additional spring affords no advantages when the system is excited by white noise. (c) 2007 Elsevier Ltd. All rights reserved.

Geração automática de hardware a partir de especificações formais: estendendo uma abordagem de tradução

Removing inconsistencies in a project is a less expensive activity when done in the early steps of design. The use of formal methods improves the understanding of systems. They have various techniques such as formal specification and verification to identify these problems in the initial stages of a project. However, the transformation from a formal specification into a programming language is a non-trivial task and error prone, specially when done manually. The aid of tools at this stage can bring great benefits to the final product to be developed. This paper proposes the extension of a tool whose focus is the automatic translation of specifications written in CSPM into Handel-C. CSP is a formal description language suitable for concurrent systems, and CSPM is the notation used in tools support. Handel-C is a programming language whose result can be compiled directly into FPGA s. Our extension increases the number of CSPM operators accepted by the tool, allowing the user to define local processes, to rename channels in a process and to use Boolean guards on external choices. In addition, we also propose the implementation of a communication protocol that eliminates some restrictions on parallel composition of processes in the translation into Handel-C, allowing communication in a same channel between multiple processes to be mapped in a consistent manner and that improper communication in a channel does not ocurr in the generated code, ie, communications that are not allowed in the system specification

Projeto e implementação em FPGA de um processador com conjunto de instrução reconfigurável utilizando VHDL

The Reconfigurable Computing is an intermediate solution at the resolution of complex problems, making possible to combine the speed of the hardware with the flexibility of the software. An reconfigurable architecture possess some goals, among these the increase of performance. The use of reconfigurable architectures to increase the performance of systems is a well known technology, specially because of the possibility of implementing certain slow algorithms in the current processors directly in hardware. Amongst the various segments that use reconfigurable architectures the reconfigurable processors deserve a special mention. These processors combine the functions of a microprocessor with a reconfigurable logic and can be adapted after the development process. Reconfigurable Instruction Set Processors (RISP) are a subgroup of the reconfigurable processors, that have as goal the reconfiguration of the instruction set of the processor, involving issues such formats, operands and operations of the instructions. This work possess as main objective the development of a RISP processor, combining the techniques of configuration of the set of executed instructions of the processor during the development, and reconfiguration of itself in execution time. The project and implementation in VHDL of this RISP processor has as intention to prove the applicability and the efficiency of two concepts: to use more than one set of fixed instructions, with only one set active in a given time, and the possibility to create and combine new instructions, in a way that the processor pass to recognize and use them in real time as if these existed in the fixed set of instruction. The creation and combination of instructions is made through a reconfiguration unit, incorporated to the processor. This unit allows the user to send custom instructions to the processor, so that later he can use them as if they were fixed instructions of the processor. In this work can also be found simulations of applications involving fixed and custom instructions and results of the comparisons between these applications in relation to the consumption of power and the time of execution, which confirm the attainment of the goals for which the processor was developed

Ethyl Carbamate Analysis in German Fruit Spirits and Brazilian Sugarcane Spirits (Cachaca): Improved Sample Cleanup with Automated Parallel Evaporation

The analysis of alcoholic beverages for the important carcinogenic contaminant ethyl carbamate is very time-consuming and expensive. Due to possible matrix interferences, sample cleanup using diatomaceous earth (Extrelut) column is required prior to gas chromatographic and mass spectrometric measurement. A limiting step in this process is the rotary evaporation of the eluate containing the analyte in organic solvents, which is currently conducted manually and requires approximately 20-30 min per sample. This paper introduces the use of a parallel evaporation device for ethyl carbamate analysis, which allows for the simultaneous evaporation of 12 samples to a specified residual volume without manual intervention. A more efficient and, less expensive analysis is therefore possible. The method validation showed no differences between the fully-automated parallel evaporation and the manual operation. The applicability was proven by analyzing authentic spirit samples from Germany, Canada and Brazil. It is interesting to note that Brazilian cachacas had a relatively high incidence for ethyl carbamate contamination (55% of all samples were above 0.15 mg/l), which may be of public health relevance and requires further evaluation.

Postoperative periodontal pain prevention using two dexamethasone medication protocols: A double-blind, parallel-group, placebo-controlled randomized clinical trial

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