921 resultados para input-output analysis
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This study focuses on the technological intensity of China's exports. It first introduces the method of decomposing gross exports by using the Asian international input–output tables. The empirical results indicate that the technological intensity of Chinese exports has been significantly overestimated due to its high dependency on import content, especially in high-technology exports, an area highly dominated by the electronic and electrical equipment sector. Furthermore, a significant portion of value added embodied in China's high-technology exports comes from services and high-technology manufacturers in neighboring economies, such as Japan, South Korea, and Taiwan.
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This study adopts the perspective of demand spillovers to provide new insights regarding Chinese domestic-regions' production position in global value chains and their associated CO2 emissions. To this end, we constructed a new type of World Input-Output Database in which China's domestic interregional input-output table for 2007 is endogenously embedded. Then, the pattern of China's regional demand spillovers across both domestic regions and countries are revealed by employing this new database. These results were further connected to endowments theory, which help to make sense of the empirical results. It is found that China's regions locate relatively upstream in GVCs, and had CO2 emissions in net exports, which were entirely predicted by the environmental extended HOV model. Our study points to micro policy instruments to combat climate change, for example, the tax reform for energy inputs that helps to change the production pattern thus has impact on trade pattern and so forth.
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We exploit the recent release of the 2005 Asian Input-Output Matrix to dress a picture of the geographic fragmentation of value added in Factory Asia from 1990 to 2005. We document 3 stylized facts. The first is that the average share of foreign value added embedded in production rose by about 7 percentage points between 1990 and 2005, from 9% to 16%. The second is that, contrary to popular belief, China's production embeds a smaller share of foreign value added than other Factory Asia countries'. Between 1990 and 2005 among Factory Asia countries China grew most after Japan as a source of value added to other countries' production. Third, country-industries at the upstream and downstream extremities of the supply chain embed a smaller share of foreign value added than those with intermediate levels of upstreamness.
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Koopman et al. (2014) developed a method to consistently decompose gross exports in value-added terms that accommodate infinite repercussions of international and inter-sector transactions. This provides a better understanding of trade in value added in global value chains than does the conventional gross exports method, which is affected by double-counting problems. However, the new framework is based on monetary input--output (IO) tables and cannot distinguish prices from quantities; thus, it is unable to consider financial adjustments through the exchange market. In this paper, we propose a framework based on a physical IO system, characterized by its linear programming equivalent that can clarify the various complexities relevant to the existing indicators and is proved to be consistent with Koopman's results when the physical decompositions are evaluated in monetary terms. While international monetary tables are typically described in current U.S. dollars, the physical framework can elucidate the impact of price adjustments through the exchange market. An iterative procedure to calculate the exchange rates is proposed, and we also show that the physical framework is also convenient for considering indicators associated with greenhouse gas (GHG) emissions.
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Using an augmented Chinese input–output table in which information about firm ownership and type of traded goods are explicitly reported, we show that ignoring firm heterogeneity causes embodied CO2 emissions in Chinese exports to be overestimated by 20% at the national level, with huge differences at the sector level, for 2007. This is because different types of firm that are allocated to the same sector of the conventional Chinese input–output table vary greatly in terms of market share, production technology and carbon intensity. This overestimation of export-related carbon emissions would be even higher if it were not for the fact that 80% of CO2 emissions embodied in exports of foreign-owned firms are, in fact, emitted by Chinese-owned firms upstream of the supply chain. The main reason is that the largest CO2 emitter, the electricity sector located upstream in Chinese domestic supply chains, is strongly dominated by Chinese-owned firms with very high carbon intensity.
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To tackle global climate change, it is desirable to reduce CO2 emissions associated with household consumption in particular in developed countries, which tend to have much higher per capita household carbon footprints than less developed countries. Our results show that carbon intensity of different consumption categories in the U.S. varies significantly. The carbon footprint tends to increase with increasing income but at a decreasing rate due to additional income being spent on less carbon intensive consumption items. This general tendency is frequently compensated by higher frequency of international trips and higher housing related carbon emissions (larger houses and more space for consumption items). Our results also show that more than 30% of CO2 emissions associated with household consumption in the U.S. occur outside of the U.S. Given these facts, the design of carbon mitigation policies should take changing household consumption patterns and international trade into account.
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Trillas et al. (1999, Soft computing, 3 (4), 197–199) and Trillas and Cubillo (1999, On non-contradictory input/output couples in Zadeh's CRI proceeding, 28–32) introduced the study of contradiction in the framework of fuzzy logic because of the significance of avoiding contradictory outputs in inference processes. Later, the study of contradiction in the framework of Atanassov's intuitionistic fuzzy sets (A-IFSs) was initiated by Cubillo and Castiñeira (2004, Contradiction in intuitionistic fuzzy sets proceeding, 2180–2186). The axiomatic definition of contradiction measure was stated in Castiñeira and Cubillo (2009, International journal of intelligent systems, 24, 863–888). Likewise, the concept of continuity of these measures was formalized through several axioms. To be precise, they defined continuity when the sets ‘are increasing’, denominated continuity from below, and continuity when the sets ‘are decreasing’, or continuity from above. The aim of this paper is to provide some geometrical construction methods for obtaining contradiction measures in the framework of A-IFSs and to study what continuity properties these measures satisfy. Furthermore, we show the geometrical interpretations motivating the measures.
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When we try to analyze and to control a system whose model was obtained only based on input/output data, accuracy is essential in the model. On the other hand, to make the procedure practical, the modeling stage must be computationally efficient. In this regard, this paper presents the application of extended Kalman filter for the parametric adaptation of a fuzzy model
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Esta Tesis aborda el diseño e implementación de aplicaciones en el campo de procesado de señal, utilizando como plataforma los dispositivos reconfigurables FPGA. Esta plataforma muestra una alta capacidad de lógica, e incorpora elementos orientados al procesado de señal, que unido a su relativamente bajo coste, la hacen ideal para el desarrollo de aplicaciones de procesado de señal cuando se requiere realizar un procesado intensivo y se buscan unas altas prestaciones. Sin embargo, el coste asociado al desarrollo en estas plataformas es elevado. Mientras que el aumento en la capacidad lógica de los dispositivos FPGA permite el desarrollo de sistemas completos, los requisitos de altas prestaciones obligan a que en muchas ocasiones se deban optimizar operadores a muy bajo nivel. Además de las restricciones temporales que imponen este tipo de aplicaciones, también tienen asociadas restricciones de área asociadas al dispositivo, lo que obliga a evaluar y verificar entre diferentes alternativas de implementación. El ciclo de diseño e implementación para estas aplicaciones se puede prolongar tanto, que es normal que aparezcan nuevos modelos de FPGA, con mayor capacidad y mayor velocidad, antes de completar el sistema, y que hagan a las restricciones utilizadas para el diseño del sistema inútiles. Para mejorar la productividad en el desarrollo de estas aplicaciones, y con ello acortar su ciclo de diseño, se pueden encontrar diferentes métodos. Esta Tesis se centra en la reutilización de componentes hardware previamente diseñados y verificados. Aunque los lenguajes HDL convencionales permiten reutilizar componentes ya definidos, se pueden realizar mejoras en la especificación que simplifiquen el proceso de incorporar componentes a nuevos diseños. Así, una primera parte de la Tesis se orientará a la especificación de diseños basada en componentes predefinidos. Esta especificación no sólo busca mejorar y simplificar el proceso de añadir componentes a una descripción, sino que también busca mejorar la calidad del diseño especificado, ofreciendo una mayor posibilidad de configuración e incluso la posibilidad de informar de características de la propia descripción. Reutilizar una componente ya descrito depende en gran medida de la información que se ofrezca para su integración en un sistema. En este sentido los HDLs convencionales únicamente proporcionan junto con la descripción del componente la interfaz de entrada/ salida y un conjunto de parámetros para su configuración, mientras que el resto de información requerida normalmente se acompaña mediante documentación externa. En la segunda parte de la Tesis se propondrán un conjunto de encapsulados cuya finalidad es incorporar junto con la propia descripción del componente, información que puede resultar útil para su integración en otros diseños. Incluyendo información de la implementación, ayuda a la configuración del componente, e incluso información de cómo configurar y conectar al componente para realizar una función. Finalmente se elegirá una aplicación clásica en el campo de procesado de señal, la transformada rápida de Fourier (FFT), y se utilizará como ejemplo de uso y aplicación, tanto de las posibilidades de especificación como de los encapsulados descritos. El objetivo del diseño realizado no sólo mostrará ejemplos de la especificación propuesta, sino que también se buscará obtener una implementación de calidad comparable con resultados de la literatura. Para ello, el diseño realizado se orientará a su implementación en FPGA, aprovechando tanto los elementos lógicos generalistas como elementos específicos de bajo nivel disponibles en estos dispositivos. Finalmente, la especificación de la FFT obtenida se utilizará para mostrar cómo incorporar en su interfaz información que ayude para su selección y configuración desde fases tempranas del ciclo de diseño. Abstract This PhD. thesis addresses the design and implementation of signal processing applications using reconfigurable FPGA platforms. This kind of platform exhibits high logic capability, incorporates dedicated signal processing elements and provides a low cost solution, which makes it ideal for the development of signal processing applications, where intensive data processing is required in order to obtain high performance. However, the cost associated to the hardware development on these platforms is high. While the increase in logic capacity of FPGA devices allows the development of complete systems, high-performance constraints require the optimization of operators at very low level. In addition to time constraints imposed by these applications, Area constraints are also applied related to the particular device, which force to evaluate and verify a design among different implementation alternatives. The design and implementation cycle for these applications can be tedious and long, being therefore normal that new FPGA models with a greater capacity and higher speed appear before completing the system implementation. Thus, the original constraints which guided the design of the system become useless. Different methods can be used to improve the productivity when developing these applications, and consequently shorten their design cycle. This PhD. Thesis focuses on the reuse of hardware components previously designed and verified. Although conventional HDLs allow the reuse of components already defined, their specification can be improved in order to simplify the process of incorporating new design components. Thus, a first part of the PhD. Thesis will focus on the specification of designs based on predefined components. This specification improves and simplifies the process of adding components to a description, but it also seeks to improve the quality of the design specified with better configuration options and even offering to report on features of the description. Hardware reuse of a component for its integration into a system largely depends on the information it offers. In this sense the conventional HDLs only provide together with the component description, the input/output interface and a set of parameters for its configuration, while other information is usually provided by external documentation. In the second part of the Thesis we will propose a formal way of encapsulation which aims to incorporate with the component description information that can be useful for its integration into other designs. This information will include features of the own implementation, but it will also support component configuration, and even information on how to configure and connect the component to carry out a function. Finally, the fast Fourier transform (FFT) will be chosen as a well-known signal processing application. It will be used as case study to illustrate the possibilities of proposed specification and encapsulation formalisms. The objective of the FFT design is not only to show practical examples of the proposed specification, but also to obtain an implementation of a quality comparable to scientific literature results. The design will focus its implementation on FPGA platforms, using general logic elements as base of the implementation, but also taking advantage of low-level specific elements available on these devices. Last, the specification of the obtained FFT will be used to show how to incorporate in its interface information to assist in the selection and configuration process early in the design cycle.
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Although numerous modelling efforts have integrated food and water considerations at the farm or river basin level, very few agro-economic models are able to jointly assess water and food policies at the global level. The present report explores the feasibility of integrating water considerations into the CAPRI model. First, a literature review of modelling approaches integrating food and water issues has been conducted. Three agro-economic models, IMPACT, WATERSIM and GLOBIOM, have been analysed in detail. In addition, biophysical and hydrological models estimating agricultural water use have also been studied, in particular the global hydrological model WATERGAP and the LISFLOOD model. Thanks to the programming approach of its supply module, CAPRI shows a high potentiality to integrate environmental indicators as well as to enter new resource constraints (land potentially irrigated, irrigation water) and input-output relationships. At least in theory, the activity-based approach of the regional programming model in CAPRI allows differentiating between rainfed and irrigated activities. The suggested approach to include water into the CAPRI model involves creating an irrigation module and a water use module. The development of the CAPRI water module will enable to provide scientific assessment on agricultural water use within the EU and to analyze agricultural pressures on water resources. The feasibility of the approach has been tested in a pilot case study including two NUTS 2 regions (Andalucia in Spain and Midi-Pyrenees in France). Preliminary results are presented, highlighting the interrelations between water and agricultural developments in Europe. As a next step, it is foreseen to further develop the CAPRI water module to account for competition between agricultural and non-agricultural water use. This will imply building a water use sub-module to compute water use balances.
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La medida de la presión sonora es un proceso de extrema importancia para la ingeniería acústica, de aplicación en numerosas áreas de esta disciplina, como la acústica arquitectónica o el control de ruido. Sobre todo en esta última, es necesario poder efectuar medidas precisas en condiciones muy diversas. Por otra parte, la ubicuidad de los dispositivos móviles inteligentes (smartphones, tabletas, etc.), dispositivos que integran potencia de procesado, conectividad, interactividad y una interfaz intuitiva en un tamaño reducido, abre la posibilidad de su uso como sistemas de medida de calidad y de coste bajo. En este Proyecto se pretende utilizar las capacidades de entrada y salida, procesado, conectividad inalámbrica y geolocalización de los dispositivos móviles basados en iOS, en concreto el iPhone, para implementar un sistema de medidas acústicas que iguale o supere las prestaciones de los sonómetros existentes en el mercado. SonoPhone permitirá, mediante la conexión de un micrófono de medida adecuado, la realización de medidas de acuerdo a las normas técnicas en vigor, así como la posibilidad de programar, configurar y almacenar o trasmitir las medidas realizadas, que además estarán geolocalizadas con el GPS integrado en el dispositivo móvil. También se permitirá enviar los datos de la medida a un almacenamiento remoto en la nube. La aplicación tiene una estructura modular en la que un módulo de adquisición de datos lee la señal del micrófono, un back-end efectúa el procesado necesario, y otros módulos permiten la calibración del dispositivo y programar y configurar las medidas, así como su almacenamiento y transmisión en red. Una interfaz de usuario (GUI) permite visualizar las medidas y efectuar las configuraciones deseadas por el usuario, todo ello en tiempo real. Además de implementar la aplicación, se ha realizado una prueba de funcionamiento para determinar si el hardware del iPhone es adecuado para la medida de la presión acústica de acuerdo a las normas internacionales. Sound pressure measurement is an extremely important process in the field of acoustic engineering, with applications in numerous subfields, like for instance building acoustics and noise control, where it is necessary to be able to accurately measure sound pressure in very diverse (and sometimes adverse) conditions. On the other hand, the growing ubiquity of mobile devices such as smartphones or tablets, which combine processing power, connectivity, interactivity and an intuitive interface in a small size, makes it possible to use these devices as quality low-cost measurement systems. This Project aims to use the input-output capabilities of iOS-based mobile devices, in particular the iPhone, together with their processing power, wireless connectivity and geolocation features, to implement an acoustic measurement system that rivals the performance of existing devices. SonoPhone allows, with the addition of an adequate measurement microphone, to carry out measurements that comply with current technical regulations, as well as programming, configuring, storing and transmitting the results of the measurement. These measurements will be geolocated using the integrated GPS, and can be transmitted effortlessly to a remote cloud storage. The application is structured in modular fashion. A data acquisition module reads the signal from the microphone, while a back-end module carries out the necessary processing. Other modules permit the device to be calibrated, or control the configuration of the measurement and its storage or transmission. A Graphical User Interface (GUI) allows visual feedback on the measurement in progress, and provides the user with real-time control over the measurement parameters. Not only an application has been developed; a laboratory test was carried out with the goal of determining if the hardware of the iPhone permits the whole system to comply with international regulations regarding sound level meters.
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The ex ante quantification of impactsis compulsory when establishing a Rural Development Program (RDP) in the European Union. Thus, the purpose of this paper is to learn how to perform it better. In order to this all of the European 2007-2013 RDPs (a total of 88) and all of their corresponding available ex ante evaluations were analyzed.Results show that less than 50% of all RDPs quantify all the impact indicators and that the most used methodology that allows the quantification of all impact indicators is Input-Output. There are two main difficulties cited for not accomplishing the impact quantification: the heterogeneity of actors and factors involved in the program impacts and the lack of needed information.These difficulties should be addressedby usingnew methods that allow approaching the complexity of the programs and by implementing a better planning that facilitatesgathering the needed information.
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This paper applies an integrated modeling approach to the case of Spain; the approach is based on a random utility-based multiregional input-output model and a road transport network model for assessing the effect of introducing longer and heavier vehicles (LHVs) on the regional consumer price index (CPI) and on the transportation system. The approach strongly supports the concept that changes in transport costs derived from the LHV allowance as well as the economic structure of regions have direct and indirect effects on the economy and on the transportation system. Results show that the introduction of LHVs might reduce prices paid by consumers for a representative basket of goods and services in the regions of Spain and would also lead to a reduction in the regional CPI. In addition, the magnitude and extent of changes in the transportation system are estimated by using the commodity-based structure of the approach to identify the effect of traffic changes on traffic flows and on pollutant emissions over the whole network.
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La obtención de energía a partir de la fusión nuclear por confinamiento magnético del plasma, es uno de los principales objetivos dentro de la comunidad científica dedicada a la energía nuclear. Desde la construcción del primer dispositivo de fusión, hasta la actualidad, se han llevado a cabo multitud de experimentos, que hoy en día, gran parte de ellos dan soporte al proyecto International Thermonuclear Experimental Reactor (ITER). El principal problema al que se enfrenta ITER, se basa en la monitorización y el control del plasma. Gracias a las nuevas tecnologías, los sistemas de instrumentación y control permiten acercarse más a la solución del problema, pero a su vez, es más complicado estandarizar los sistemas de adquisición de datos que se usan, no solo en ITER, sino en otros proyectos de igual complejidad. Desarrollar nuevas implementaciones hardware y software bajo los requisitos de los diagnósticos definidos por los científicos, supone una gran inversión de tiempo, retrasando la ejecución de nuevos experimentos. Por ello, la solución que plantea esta tesis, consiste en la definición de una metodología de diseño que permite implementar sistemas de adquisición de datos inteligentes y su fácil integración en entornos de fusión para la implementación de diagnósticos. Esta metodología requiere del uso de los dispositivos Reconfigurable Input/Output (RIO) y Flexible RIO (FlexRIO), que son sistemas embebidos basados en tecnología Field-Programmable Gate Array (FPGA). Para completar la metodología de diseño, estos dispositivos van a ser soportados por un software basado en EPICS Device Support utilizando la tecnología EPICS software asynDriver. Esta metodología se ha evaluado implementando prototipos para los controladores rápidos de planta de ITER, tanto para casos prácticos de ámbito general como adquisición de datos e imágenes, como para casos concretos como el diagnóstico del fission chamber, implementando pre-procesado en tiempo real. Además de casos prácticos, esta metodología se ha utilizado para implementar casos reales, como el Ion Source Hydrogen Positive (ISHP), desarrollada por el European Spallation Source (ESS Bilbao) y la Universidad del País Vasco. Finalmente, atendiendo a las necesidades que los experimentos en los entornos de fusión requieren, se ha diseñado un mecanismo mediante el cual los sistemas de adquisición de datos, que pueden ser implementados mediante la metodología de diseño propuesta, pueden integrar un reloj hardware capaz de sincronizarse con el protocolo IEEE1588-V2, permitiendo a estos, obtener los TimeStamps de las muestras adquiridas con una exactitud y precisión de decenas de nanosegundos y realizar streaming de datos con TimeStamps. ABSTRACT Fusion energy reaching by means of nuclear fusion plasma confinement is one of the main goals inside nuclear energy scientific community. Since the first fusion device was built, many experiments have been carried out and now, most of them give support to the International Thermonuclear Experimental Reactor (ITER) project. The main difficulty that ITER has to overcome is the plasma monitoring and control. Due to new technologies, the instrumentation and control systems allow an approaching to the solution, but in turn, the standardization of the used data acquisition systems, not only in ITER but also in other similar projects, is more complex. To develop new hardware and software implementations under scientific diagnostics requirements, entail time costs, delaying new experiments execution. Thus, this thesis presents a solution that consists in a design methodology definition, that permits the implementation of intelligent data acquisition systems and their easy integration into fusion environments for diagnostic purposes. This methodology requires the use of Reconfigurable Input/Output (RIO) and Flexible RIO (FlexRIO) devices, based on Field-Programmable Gate Array (FPGA) embedded technology. In order to complete the design methodology, these devices are going to be supported by an EPICS Device Support software, using asynDriver technology. This methodology has been evaluated implementing ITER PXIe fast controllers prototypes, as well as data and image acquisition, so as for concrete solutions like the fission chamber diagnostic use case, using real time preprocessing. Besides of these prototypes solutions, this methodology has been applied for the implementation of real experiments like the Ion Source Hydrogen Positive (ISHP), developed by the European Spallation Source and the Basque country University. Finally, a hardware mechanism has been designed to integrate a hardware clock into RIO/FlexRIO devices, to get synchronization with the IEEE1588-V2 precision time protocol. This implementation permits to data acquisition systems implemented under the defined methodology, to timestamp all data acquired with nanoseconds accuracy, permitting high throughput timestamped data streaming.
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El proyecto fin de carrera de herramienta de apoyo a la docencia en Sistemas Operativos quiere ayudar al alumno a entender el funcionamiento de un planificador a corto plazo. Lo hace mediante una representación gráfica de procesos que ocupan o el procesador o distintas unidades de entrada/salida mientras transcurre el tiempo. El tiempo está dividido en ciclos de reloj de un procesador, a lo que a continuación se referirá como unidades de tiempo. Los procesos están definidos por su nombre, la instante de entrada que entran al sistema, su prioridad y la secuencia de unidades de tiempo en el procesador y unidades de entrada/salida que necesitan para terminar su trabajo. El alumno puede configurar el sistema a su gusto en cuanto al número y comportamiento de las unidades de entrada/salida. Puede definir que una unidad solo permita acceso exclusivo a los procesos, es decir que solo un proceso puede ocuparla simultáneamente, o que permita el acceso múltiple a sus recursos. El alumno puede construir un planificador a corto plazo propio, integrarlo en el sistema y ver cómo se comporta. Se debe usar la interfaz Java proporcionada para su construcción. La aplicación muestra datos estadísticos como por ejemplo la eficiencia del sistema (el tiempo activo de la CPU dividido por el tiempo total de la simulación), tiempos de espera de los procesos, etc. Se calcula después de cada unidad de tiempo para que el alumno pueda ver el momento exacto donde la simulación tomó un giro inesperado. La aplicación está compuesta por un motor de simulación que contiene toda la lógica y un conjunto de clases que forman la interfaz gráfica que se presenta al usuario. Estos dos componentes pueden ser reemplazados siempre y cuando se mantenga la definición de sus conectores igual. La aplicación la he hecho de manejo muy simple e interfaz fácil de comprender para que el alumno pueda dedicar todo su tiempo a probar distintas configuraciones y situaciones y así entender mejor la asignatura. ABSTRACT. The project is called “Tool to Support Teaching of the Subject Operating Systems” and is an application that aims to help students understand on a deeper level the inner workings of how an operating system handles multiple processes in need of CPU time by the means of a short-term planning algorithm. It does so with a graphical representation of the processes that occupy the CPU and different input/output devices as time passes by. Time is divided in CPU cycles, from now on referred to as time units. The processes are defined by their name, the moment they enter the system, their priority and the sequence of time units they need to finish their job. The student can configure the system by changing the number and behavior of the input/output devices. He or she can define whether a device should only allow exclusive access, i.e. only one process can occupy it at any given time, or if it should allow multiple processes to access its resources. The student can build a planning algorithm of his or her own and easily integrate it into the system to see how it behaves. The provided Java interface and the programming language Java should be used to build it. The application shows statistical data, e.g. the efficiency of the system (active CPU time divided by total simulation time) and time spent by the processes waiting in queues. The data are calculated after passing each time unit in order for the student to see the exact moment where the simulation took an unexpected turn. The application is comprised of a simulation motor, which handles all the logic, and a set of classes, which is the graphical user interface. These two parts can be replaced individually if the definition of the connecting interfaces stays the same. I have made the application to be very easy to use and with an easy to understand user interface so the student can spend all of his or her time trying out different configurations and scenarios in order to understand the subject better.