Els continguts digitals i la teoria de les intel??lig??ncies m??ltiples

Resumen basado en el de la publicaci??n

Comparison of speech processor MAP minimum (T) and maximum (C) levels with psychophysical thresholds and maximum acceptable loudness levels in users of the Nucleus 22 cochlear implant system

This paper discusses the Nucleus 22 cochlear implant.

Trust and governance of global value chains: The case of a Brazilian beef processor

Purpose - The purpose of this paper is to offer an exploratory case study comparing one Brazilian beef processor's relationships supplying two different distribution channels, an EU importer and an EU retail chain operating in Brazil. Design/methodology/approach - The paper begins with a short review of global value chains and the recent literature on trust. It gives the background to the Brazilian beef chain and presents data obtained through in-depth interviews, annual reports and direct observation with the Brazilian beef processor, the EU importer and the retailer. The interviews were conducted with individual firms, but the analysis places them in a chain context, identifying the links and relationships between the agents of the chains and aiming to describe each distribution channel. Findings - Executive chain governance exercised by the domestic retailer stimulates technical upgrading and transferring of best practices to local. suppliers. Consequently, this kind of relationship results in more trust within the global value chain. Practical implications - There are difficulties and challenges facing this Brazilian beef processor that are party related to the need to comply with increasingly complex and demanding food safety and food quality standards. There is still a gap between practices adopted for the export market and practices adopted locally. The strategies of transnational retailers in offering differentiated beef should be taken in account. Originality/value - The research outlines an interdisciplinary framework able to explain chain relationships and the kind of trust that emerges in relationships between EU importer/retail and a developing country supplier.

Improving CS-4 user data rate in GPRS enabled devices by using a BLER co-processor

The General Packet Radio Service (GPRS) was developed to allow packet data to be transported efficiently over an existing circuit switched radio network. The main applications for GPRS are in transporting IP datagram’s from the user’s mobile Internet browser to and from the Internet, or in telemetry equipment. A simple Error Detection and Correction (EDC) scheme to improve the GPRS Block Error Rate (BLER) performance is presented, particularly for coding scheme 4 (CS-4), however gains in other coding schemes are seen. For every GPRS radio block that is corrected by the EDC scheme, the block does not need to be retransmitted releasing bandwidth in the channel, improving throughput and the user’s application data rate. As GPRS requires intensive processing in the baseband, a viable hardware solution for a GPRS BLER co-processor is discussed that has been currently implemented in a Field Programmable Gate Array (FPGA) and presented in this paper.

Implementing intelligent cores using processor virtualization for fault tolerance

Processor virtualization for process migration in distributed parallel computing systems has formed a significant component of research on load balancing. In contrast, the potential of processor virtualization for fault tolerance has been addressed minimally. The work reported in this paper is motivated towards extending concepts of processor virtualization towards ‘intelligent cores’ as a means to achieve fault tolerance in distributed parallel computing systems. Intelligent cores are an abstraction of the hardware processing cores, with the incorporation of cognitive capabilities, on which parallel tasks can be executed and migrated. When a processing core executing a task is predicted to fail the task being executed is proactively transferred onto another core. A parallel reduction algorithm incorporating concepts of intelligent cores is implemented on a computer cluster using Adaptive MPI and Charm ++. Preliminary results confirm the feasibility of the approach.

Adaptive alarm processor for fault diagnosis on power transmission networks

The authors describe a learning classifier system (LCS) which employs genetic algorithms (GA) for adaptive online diagnosis of power transmission network faults. The system monitors switchgear indications produced by a transmission network, reporting fault diagnoses on any patterns indicative of faulted components. The system evaluates the accuracy of diagnoses via a fault simulator developed by National Grid Co. and adapts to reflect the current network topology by use of genetic algorithms.

FAMOUS, faster: using parallel computing techniques to accelerate the FAMOUS/HadCM3 climate model with a focus on the radiative transfer algorithm

We have optimised the atmospheric radiation algorithm of the FAMOUS climate model on several hardware platforms. The optimisation involved translating the Fortran code to C and restructuring the algorithm around the computation of a single air column. Instead of the existing MPI-based domain decomposition, we used a task queue and a thread pool to schedule the computation of individual columns on the available processors. Finally, four air columns are packed together in a single data structure and computed simultaneously using Single Instruction Multiple Data operations. The modified algorithm runs more than 50 times faster on the CELL’s Synergistic Processing Elements than on its main PowerPC processing element. On Intel-compatible processors, the new radiation code runs 4 times faster. On the tested graphics processor, using OpenCL, we find a speed-up of more than 2.5 times as compared to the original code on the main CPU. Because the radiation code takes more than 60% of the total CPU time, FAMOUS executes more than twice as fast. Our version of the algorithm returns bit-wise identical results, which demonstrates the robustness of our approach. We estimate that this project required around two and a half man-years of work.

Study of the audio coding algorithm of the MPEG-4 AAC standard and comparison among implementations of modules of the algorithm

Audio coding is used to compress digital audio signals, thereby reducing the amount of bits needed to transmit or to store an audio signal. This is useful when network bandwidth or storage capacity is very limited. Audio compression algorithms are based on an encoding and decoding process. In the encoding step, the uncompressed audio signal is transformed into a coded representation, thereby compressing the audio signal. Thereafter, the coded audio signal eventually needs to be restored (e.g. for playing back) through decoding of the coded audio signal. The decoder receives the bitstream and reconverts it into an uncompressed signal. ISO-MPEG is a standard for high-quality, low bit-rate video and audio coding. The audio part of the standard is composed by algorithms for high-quality low-bit-rate audio coding, i.e. algorithms that reduce the original bit-rate, while guaranteeing high quality of the audio signal. The audio coding algorithms consists of MPEG-1 (with three different layers), MPEG-2, MPEG-2 AAC, and MPEG-4. This work presents a study of the MPEG-4 AAC audio coding algorithm. Besides, it presents the implementation of the AAC algorithm on different platforms, and comparisons among implementations. The implementations are in C language, in Assembly of Intel Pentium, in C-language using DSP processor, and in HDL. Since each implementation has its own application niche, each one is valid as a final solution. Moreover, another purpose of this work is the comparison among these implementations, considering estimated costs, execution time, and advantages and disadvantages of each one.

Dressing monitoring with a digital signal processor

Grinding is a finishing process in machining operations, and the topology of the grinding tool is responsible for producing the desired result on the surface of the machined material The tool topology is modeled in the dressing process and precision is therefore extremely important This study presents a solution in the monitoring of the dressing process, using a digital signal processor (DSP) operating in real time to detect the optimal dressing moment To confirm the monitoring efficiency by DSP, the results were compared with those of a data acquisition system (DAQ) and offline processing The method employed here consisted of analyzing the acoustic emission and electrical power signal by applying the DPO and DPKS parameters The analysis of the results allowed us to conclude that the application of the DPO and DPKS parameters can be substituted by processing of the mean acoustic emission signal, thus reducing the computational effort

Noise reduction in speech signals using a TMS320C31 digital signal processor

This paper describes a speech enhancement system (SES) based on a TMS320C31 digital signal processor (DSP) for real-time application. The SES algorithm is based on a modified spectral subtraction method and a new speech activity detector (SAD) is used. The system presents a medium computational load and a sampling rate up to 18 kHz can be used. The goal is load and a sampling rate up to 18 kHz can be used. The goal is to use it to reduce noise in an analog telephone line.

Towards a java bytecodes compiler for nios II soft-core processor

Reconfigurable computing is one of the most recent research topics in computer science. The Altera - Nios II soft-core processor can be included in a large set of reconfigurable architectures, especially because it is designed in software, allowing it to be configured according to the application. The recent growth in applications that demand reconfigurable computing made necessary the building of compilers that translate high level languages source codes into reconfigurable devices instruction sets. In this paper we present a compiler that takes as input the bytecodes generated by a Java front-end compiler and generates a set of instructions that attends to the Nios II processor instruction set rules. Our work shows how we process Java bytecodes to the intermediate code, in the Nios II instructions format, and build the control flow and the control dependence graphs. © 2009 IEEE.