Capacitive electrolyte-insulator-semiconductor structures functionalised with a polyelectrolyte/enzyme multilayer: New strategy for enhanced field-effect biosensing

A novel strategy for enhanced field-effect biosensing using capacitive electrolyte-insulator-semiconductor (EIS) structures functionalised with pH-responsive weak polyelectrolyte/enzyme or dendrimer/enzyme multilayers is presented. The feasibility of the proposed approach is exemplarily demonstrated by realising a penicillin biosensor based on a capacitive p-Si-SiO(2) EIS structure functionalised with a poly(allylamine hydrochloride) (PAH)/penicillinase and a poly(amidoamine) dendrimer/penicillinase multilayer. The developed sensors response to changes in both the local pH value near the gate surface and the charge of macromolecules induced via enzymatic reaction, resulting in a higher sensitivity. For comparison, an EIS penicillin biosensor with adsorptively immobilised penicillinase has been also studied. The highest penicillin sensitivity of 100 mV/dec has been observed for the EIS sensor functionalised with the PAH/penicillinase multilayer. The lower and upper detection limit was around 20 mu M and 10 mM, respectively. In addition, an incorporation of enzymes in a multilayer prepared by layer-by-layer technique provides a larger amount of immobilised enzymes per sensor area, reduces enzyme leaching effects and thus, enhances the biosensor lifetime (the loss of penicillin sensitivity after 2 months was 10-12%). (C) 2010 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

Low-Frequency Noise in Field-Effect Devices Functionalized With Dendrimer/Carbon-Nanotube Multilayers

Low-frequency noise in an electrolyte-insulator- semiconductor (EIS) structure functionalized with multilayers of polyamidoamine (PAMAM) dendrimer and single-walled carbon nanotubes (SWNT) is studied. The noise spectral density exhibits 1/f(gamma) dependence with the power factor of gamma approximate to 0.8 and gamma = 0.8-1.8 for the bare and functionalized EIS sensor, respectively. The gate-voltage noise spectral density is practically independent of the pH value of the solution and increases with increasing gate voltage or gate-leakage current. It has been revealed that functionalization of an EIS structure with a PAMAM/SWNTs multilayer leads to an essential reduction of the 1/f noise. To interpret the noise behavior in bare and functionalized EIS devices, a gate-current noise model for capacitive EIS structures based on an equivalent flatband-voltage fluctuation concept has been developed.

A III-V channel field effect transistor for non-classical CMOS: process optimisation for improved gate stack function

This thesis describes a collection of studies into the electrical response of a III-V MOS stack comprising metal/GaGdO/GaAs layers as a function of fabrication process variables and the findings of those studies. As a result of this work, areas of improvement in the gate process module of a III-V heterostructure MOSFET were identified. Compared to traditional bulk silicon MOSFET design, one featuring a III-V channel heterostructure with a high-dielectric-constant oxide as the gate insulator provides numerous benefits, for example: the insulator can be made thicker for the same capacitance, the operating voltage can be made lower for the same current output, and improved output characteristics can be achieved without reducing the channel length further. It is known that transistors composed of III-V materials are most susceptible to damage induced by radiation and plasma processing. These devices utilise sub-10 nm gate dielectric films, which are prone to contamination, degradation and damage. Therefore, throughout the course of this work, process damage and contamination issues, as well as various techniques to mitigate or prevent those have been investigated through comparative studies of III-V MOS capacitors and transistors comprising various forms of metal gates, various thicknesses of GaGdO dielectric, and a number of GaAs-based semiconductor layer structures. Transistors which were fabricated before this work commenced, showed problems with threshold voltage control. Specifically, MOSFETs designed for normally-off (VTH > 0) operation exhibited below-zero threshold voltages. With the results obtained during this work, it was possible to gain an understanding of why the transistor threshold voltage shifts as the gate length decreases and of what pulls the threshold voltage downwards preventing normally-off device operation. Two main culprits for the negative VTH shift were found. The first was radiation damage induced by the gate metal deposition process, which can be prevented by slowing down the deposition rate. The second was the layer of gold added on top of platinum in the gate metal stack which reduces the effective work function of the whole gate due to its electronegativity properties. Since the device was designed for a platinum-only gate, this could explain the below zero VTH. This could be prevented either by using a platinum-only gate, or by matching the layer structure design and the actual gate metal used for the future devices. Post-metallisation thermal anneal was shown to mitigate both these effects. However, if post-metallisation annealing is used, care should be taken to ensure it is performed before the ohmic contacts are formed as the thermal treatment was shown to degrade the source/drain contacts. In addition, the programme of studies this thesis describes, also found that if the gate contact is deposited before the source/drain contacts, it causes a shift in threshold voltage towards negative values as the gate length decreases, because the ohmic contact anneal process affects the properties of the underlying material differently depending on whether it is covered with the gate metal or not. In terms of surface contamination; this work found that it causes device-to-device parameter variation, and a plasma clean is therefore essential. This work also demonstrated that the parasitic capacitances in the system, namely the contact periphery dependent gate-ohmic capacitance, plays a significant role in the total gate capacitance. This is true to such an extent that reducing the distance between the gate and the source/drain ohmic contacts in the device would help with shifting the threshold voltages closely towards the designed values. The findings made available by the collection of experiments performed for this work have two major applications. Firstly, these findings provide useful data in the study of the possible phenomena taking place inside the metal/GaGdO/GaAs layers and interfaces as the result of chemical processes applied to it. In addition, these findings allow recommendations as to how to best approach fabrication of devices utilising these layers.

Extension of the impedance field method to the noise analysis of a semiconductor junction: Analytical approach

We present an analytical procedure to perform the local noise analysis of a semiconductor junction when both the drift and diffusive parts of the current are important. The method takes into account space-inhomogeneous and hot-carriers conditions in the framework of the drift-diffusion model, and it can be effectively applied to the local noise analysis of different devices: n+nn+ diodes, Schottky barrier diodes, field-effect transistors, etc., operating under strongly inhomogeneous distributions of the electric field and charge concentration

Extension of the impedance field method to the noise analysis of a semiconductor junction: Analytical approach

We present an analytical procedure to perform the local noise analysis of a semiconductor junction when both the drift and diffusive parts of the current are important. The method takes into account space-inhomogeneous and hot-carriers conditions in the framework of the drift-diffusion model, and it can be effectively applied to the local noise analysis of different devices: n+nn+ diodes, Schottky barrier diodes, field-effect transistors, etc., operating under strongly inhomogeneous distributions of the electric field and charge concentration

Electrical characterization of poly(amide-imide) for application in organic field effect devices

The admittance spectra and current-voltage (I-V) characteristics are reported of metal-insulator-metal (MIM) and metal-insulator-semiconductor (MIS) capacitors employing cross-linked poly(amide-imide) (c-PAI) as the insulator and poly(3-hexylthiophene) (P3HT) as the active semiconductor. The capacitance of the MIM devices are constant in the frequency range from 10 Hz to 100 kHz, with tan delta values as low as 7 x 10(-3) over most of the range. Except at the lowest voltages, the I-V characteristics are well-described by the Schottky equation for thermal emission of electrons from the electrodes into the insulator. The admittance spectra of the MIS devices displayed a classic Maxwell-Wagner frequency response from which the transverse bulk hole mobility was estimated to be similar to 2 x 10(-5) cm(2) V(-1)s(-1) or similar to 5 x 10(-8) cm(2) V(-1)s(-1) depending on whether or not the surface of the insulator had been treated with hexamethyldisilazane (HMDS) prior to deposition of the P3HT. From the maximum loss observed in admittance-voltage plots, the interface trap density was estimated to be similar to 5 x 10(10) cm(-2) eV(-1) or similar to 9 x 10(10) cm(-2) eV(-1) again depending whether or not the insulator was treated with HMDS. We conclude, therefore, that HMDS plays a useful role in promoting order in the P3HT film as well as reducing the density of interface trap states. Although interposing the P3HT layer between the insulator and the gold electrode degrades the insulating properties of the c-PAI, nevertheless, they remain sufficiently good for use in organic electronic devices. (c) 2012 Elsevier B.V. All rights reserved.

The development of planar high-K/III-V p-channel MOSFETs for post-silicon CMOS

Conventional Si complementary-metal-oxide-semiconductor (CMOS) scaling is fast approaching its limits. The extension of the logic device roadmap for future enhancements in transistor performance requires non-Si materials and new device architectures. III-V materials, due to their superior electron transport properties, are well poised to replace Si as the channel material beyond the 10nm technology node to mitigate the performance loss of Si transistors from further reductions in supply voltage to minimise power dissipation in logic circuits. However several key challenges, including a high quality dielectric/III-V gate stack, a low-resistance source/drain (S/D) technology, heterointegration onto a Si platform and a viable III-V p-metal-oxide-semiconductor field-effect-transistor (MOSFET), need to be addressed before III-Vs can be employed in CMOS. This Thesis specifically addressed the development and demonstration of planar III-V p-MOSFETs, to complement the n-MOSFET, thereby enabling an all III-V CMOS technology to be realised. This work explored the application of InGaAs and InGaSb material systems as the channel, in conjunction with Al2O3/metal gate stacks, for p-MOSFET development based on the buried-channel flatband device architecture. The body of work undertaken comprised material development, process module development and integration into a robust fabrication flow for the demonstration of p-channel devices. The parameter space in the design of the device layer structure, based around the III-V channel/barrier material options of In_x≥0.53Ga_1-xAs/In_0.52Al_0.48As and In_x≥0.1Ga_1-xSb/AlSb, was systematically examined to improve hole channel transport. A mobility of 433 cm²/Vs, the highest room temperature hole mobility of any InGaAs quantum-well channel reported to date, was obtained for the In_0.85Ga_0.15As (2.1% strain) structure. S/D ohmic contacts were developed based on thermally annealed Au/Zn/Au metallisation and validated using transmission line model test structures. The effects of metallisation thickness, diffusion barriers and de-oxidation conditions were examined. Contacts to InGaSb-channel structures were found to be sensitive to de-oxidation conditions. A fabrication process, based on a lithographically-aligned double ohmic patterning approach, was realised for deep submicron gate-to-source/drain gap (L_side) scaling to minimise the access resistance, thereby mitigating the effects of parasitic S/D series resistance on transistor performance. The developed process yielded gaps as small as 20nm. For high-k integration on GaSb, ex-situ ammonium sulphide ((NH₄)₂S) treatments, in the range 1%-22%, for 10min at 295K were systematically explored for improving the electrical properties of the Al₂O₃/GaSb interface. Electrical and physical characterisation indicated the 1% treatment to be most effective with interface trap densities in the range of 4 - 10×10¹²cm^-2eV^-1 in the lower half of the bandgap. An extended study, comprising additional immersion times at each sulphide concentration, was further undertaken to determine the surface roughness and the etching nature of the treatments on GaSb. A number of p-MOSFETs based on III-V-channels with the most promising hole transport and integration of the developed process modules were successfully demonstrated in this work. Although the non-inverted InGaAs-channel devices showed good current modulation and switch-off characteristics, several aspects of performance were non-ideal; depletion-mode operation, modest drive current (I_d,sat=1.14mA/mm), double peaked transconductance (g_m=1.06mS/mm), high subthreshold swing (SS=301mV/dec) and high on-resistance (R_on=845kΩ.μm). Despite demonstrating substantial improvement in the on-state metrics of I_d,sat (11×), g_m (5.5×) and R_on (5.6×), inverted devices did not switch-off. Scaling gate-to-source/drain gap (L_side) from 1μm down to 70nm improved I_d,sat (72.4mA/mm) by a factor of 3.6 and gm (25.8mS/mm) by a factor of 4.1 in inverted InGaAs-channel devices. Well-controlled current modulation and good saturation behaviour was observed for InGaSb-channel devices. In the on-state In_0.3Ga_0.7Sb-channel (I_d,sat=49.4mA/mm, g_m=12.3mS/mm, R_on=31.7kΩ.μm) and In_0.4Ga_0.6Sb-channel (I_d,sat=38mA/mm, g_m=11.9mS/mm, R_on=73.5kΩ.μm) devices outperformed the InGaAs-channel devices. However the devices could not be switched off. These findings indicate that III-V p-MOSFETs based on InGaSb as opposed to InGaAs channels are more suited as the p-channel option for post-Si CMOS.

Field effect and light-assisted a-Si:H sensors for detection of ions in solution

In this paper we present an amorphous silicon device that can be used in two operation modes to measure the concentration of ions in solution. While crystalline devices present a higher sensitivity, their amorphous counterpart present a much lower fabrication cost, thus enabling the production of cheap disposable sensors for use, for example, in the food industry. The devices were fabricated on glass substrates by the PECVD technique in the top gate configuration, where the metallic gate is replaced by an electrolytic solution with an immersed Ag/AgCl reference electrode. Silicon nitride is used as gate dielectric enhancing the sensitivity and passivation layer used to avoid leakage and electrochemical reactions. In this article we report on the semiconductor unit, showing that the device can be operated in a light-assisted mode, where changes in the pH produce changes on the measured ac photocurrent. In alternative the device can be operated as a conventional ion selective field effect device where changes in the pH induce changes in the transistor's threshold voltage.

Towards printed carbon nanotube transistors on paper substrates

This thesis reports the work performed in the optimization of deposition parameters of Multi – Walled Carbon Nanotubes (MWCNT) targeting the development of a Field Effect Transistors (FET) on paper substrates. The CNTs were dispersed in a water solution with sodium dodecyl sulphate (SDS) through ultrasonication, ultrasonic bath and a centrifugation to remove the supernatant and have a homogeneous solution. Several deposition tests were performed using different types of CNTs, dis-persants, papers substrates and deposition techniques, such as spray coating and inkjet printing. The characterization of CNTs was made by Scanning Electron Microscopy (SEM) and Hall Effect. The most suitable CNT coatings able to be used as semiconductor in FETs were deposited by spray coat-ing on a paper substrate with hydrophilic nanoporous surface (FS2) at 100 ºC, 4 bar, 10 cm height, 5 second of deposition time and 90 seconds of drying between steps (4 layers of CNTs were deposited). Planar electrolyte gated FETs were produced with these layers using gold-nickel gate, source and drain electrodes. Despite the small current modulation (Ion/Ioff ratio of 1.8) one of these devices have p-type conduction with a field effect mobility of 1.07 cm2/V.s.

Research and development of III-V semiconductor surfaces for improved device interfaces

This thesis is devoted to understanding and improving technologically important III-V compound semiconductor (e.g. GaAs, InAs, and InSb) surfaces and interfaces for devices. The surfaces and interfaces of crystalline III-V materials have a crucial role in the operation of field-effect-transistors (FET) and highefficiency solar-cells, for instance. However, the surfaces are also the most defective part of the semiconductor material and it is essential to decrease the amount of harmful surface or interface defects for the next-generation III-V semiconductor device applications. Any improvement in the crystal ordering at the semiconductor surface reduces the amount of defects and increases the material homogeneity. This is becoming more and more important when the semiconductor device structures decrease to atomic-scale dimensions. Toward that target, the effects of different adsorbates (i.e., Sn, In, and O) on the III-V surface structures and properties have been investigated in this work. Furthermore, novel thin-films have been synthesized, which show beneficial properties regarding the passivation of the reactive III-V surfaces. The work comprises ultra-high-vacuum (UHV) environment for the controlled fabrication of atomically ordered III-V(100) surfaces. The surface sensitive experimental methods [low energy electron diffraction (LEED), scanning tunneling microscopy/spectroscopy (STM/STS), and synchrotron radiation photoelectron spectroscopy (SRPES)] and computational density-functionaltheory (DFT) calculations are utilized for elucidating the atomic and electronic properties of the crucial III-V surfaces. The basic research results are also transferred to actual device tests by fabricating metal-oxide-semiconductor capacitors and utilizing the interface sensitive measurement techniques [capacitance voltage (CV) profiling, and photoluminescence (PL) spectroscopy] for the characterization. This part of the thesis includes the instrumentation of home-made UHV-compatible atomic-layer-deposition (ALD) reactor for growing good quality insulator layers. The results of this thesis elucidate the atomic structures of technologically promising Sn- and In-stabilized III-V compound semiconductor surfaces. It is shown that the Sn adsorbate induces an atomic structure with (1×2)/(1×4) surface symmetry which is characterized by Sn-group III dimers. Furthermore, the stability of peculiar ζa structure is demonstrated for the GaAs(100)-In surface. The beneficial effects of these surface structures regarding the crucial III-V oxide interface are demonstrated. Namely, it is found that it is possible to passivate the III-V surface by a careful atomic-scale engineering of the III-V surface prior to the gate-dielectric deposition. The thin (1×2)/(1×4)-Sn layer is found to catalyze the removal of harmful amorphous III-V oxides. Also, novel crystalline III-V-oxide structures are synthesized and it is shown that these structures improve the device characteristics. The finding of crystalline oxide structures is exploited by solving the atomic structure of InSb(100)(1×2) and elucidating the electronic structure of oxidized InSb(100) for the first time.

Spectroscopic Studies of III-V Semiconductor Materials for Improved Devices

Defects in semiconductor crystals and at their interfaces usually impair the properties and the performance of devices. These defects include, for example, vacancies (i.e., missing crystal atoms), interstitials (i.e., extra atoms between the host crystal sites), and impurities such as oxygen atoms. The defects can decrease (i) the rate of the radiative electron transition from the conduction band to the valence band, (ii) the amount of charge carriers, and (iii) the mobility of the electrons in the conduction band. It is a common situation that the presence of crystal defects can be readily concluded as a decrease in the luminescence intensity or in the current flow for example. However, the identification of the harmful defects is not straightforward at all because it is challenging to characterize local defects with atomic resolution and identification. Such atomic-scale knowledge is however essential to find methods for reducing the amount of defects in energy-efficient semiconductor devices. The defects formed in thin interface layers of semiconductors are particularly difficult to characterize due to their buried and amorphous structures. Characterization methods which are sensitive to defects often require well-defined samples with long range order. Photoelectron spectroscopy (PES) combined with photoluminescence (PL) or electrical measurements is a potential approach to elucidate the structure and defects of the interface. It is essential to combine the PES with complementary measurements of similar samples to relate the PES changes to changes in the interface defect density. Understanding of the nature of defects related to III-V materials is relevant to developing for example field-effect transistors which include a III-V channel, but research is still far from complete. In this thesis, PES measurements are utilized in studies of various III-V compound semiconductor materials. PES is combined with photoluminescence measurements to study the SiO2/GaAs, SiNx/GaAs and BaO/GaAs interfaces. Also the formation of novel materials InN and photoluminescent GaAs nanoparticles are studied. Finally, the formation of Ga interstitial defects in GaAsN is elucidated by combining calculational results with PES measurements.

Associating biosensing properties with the morphological structure of multilayers containing carbon nanotubes on field-effect devices

The control of molecular architecture provided by the layer-by-layer (LbL) technique has led to enhanced biosensors, in which advantageous features of distinct materials can be combined. Full optimization of biosensing performance, however, is only reached if the film morphology is suitable for the principle of detection of a specific biosensor. In this paper, we report a detailed morphology analysis of LbL films made with alternating layers of single-walled carbon nanotubes (SWNTs) and polyamidoamine (PAMAM) dendrimers, which were then covered with a layer of penicillinase (PEN). An optimized performance to detect penicillin G was obtained with 6-bilayer SWNT/PAMAM LbL films deposited on p-Si-SiO(2)-Ta(2)O(5) chips, used in biosensors based on a capacitive electrolyte-insulator-semiconductor (EIS) and a light-addressable potentiometric sensor (LAPS) structure, respectively. Field-emission scanning electron microscopy (FESEM) and atomic force microscopy (AFM) images indicated that the LbL films were porous, with a large surface area due to interconnection of SWNT into PAMAM layers. This morphology was instrumental for the adsorption of a larger quantity of PEN, with the resulting LbL film being highly stable. The experiments to detect penicillin were performed with constant-capacitance (Con Cap) and constant-current (CC) measurements for EIS and LAPS sensors, respectively, which revealed an enhanced detection signal and sensitivity of ca. 100 mV/decade for the field-effect sensors modified with the PAMAM/SWNT LbL film. It is concluded that controlling film morphology is essential for an enhanced performance of biosensors, not only in terms of sensitivity but also stability and response time. (C) 2010 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

Carbon nanotubes in nanostructured films: Potential application as amperometric and potentiometric field-effect (bio-)chemical sensors

The assembly of carbon nanotubes (CNTs) into nanostructured films is attractive for producing functionalized hybrid materials and (bio-)chemical sensors, but this requires experimental methods that allow for control of molecular architecturcs. In this study, we exploit the layer-by-layer (LbL) technique to obtain two types of sensors incorporating CNTs. In the first, LbL films of alternating layers of multi-walled carbon nanotubes (MWNTs) dispersed in polyarninoamide (PAMAM) dendrimers and nickel phthalocyanine (NiTsPc) were used in amperometric detection of the neurotransmitter dopamine (DA). The electrochemical properties evaluated with cyclic voltammetry indicated that the incorporation of MWNTs in the PAMAM-NT/NiTsPc LbL films led to a 3-fold increase in the peak current, in addition to a decrease of 50 mV in the oxidation potential of DA. The latter allowed detection of DA even in the presence of ascorbic acid (AA), a typical interferent for DA. Another LbL film was obtained with layers of PAMAM and single-walled carbon nanotubes (SWNTs) employed in field-effect-devices using a capacitive electrolyte-insulator-semiconductor structure (EIS). The adsorption of the film components was monitored by measuring the flat-band voltage shift in capacitance-voltage (C-P) curves, caused by the charges from the components. Constant capacitance (ConCap) measurements showed that the EISPAMAM/SWNT film displayed a high pH sensitivity (ca. 54.5 mV/pH), being capable of detecting penicillin G between 10(-4) mol L(-1) and 10(-2) mol L-1, when a layer of penicillinase was adsorbed atop the PAMAM/SWNT film. (C) 2009 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Electrical characterization of poly(amide-imide) for application in organic field effect devices

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)