Semantic coordination through programmable Tuple spaces

Two of the main features of today complex software systems like pervasive computing systems and Internet-based applications are distribution and openness. Distribution revolves around three orthogonal dimensions: (i) distribution of control|systems are characterised by several independent computational entities and devices, each representing an autonomous and proactive locus of control; (ii) spatial distribution|entities and devices are physically distributed and connected in a global (such as the Internet) or local network; and (iii) temporal distribution|interacting system components come and go over time, and are not required to be available for interaction at the same time. Openness deals with the heterogeneity and dynamism of system components: complex computational systems are open to the integration of diverse components, heterogeneous in terms of architecture and technology, and are dynamic since they allow components to be updated, added, or removed while the system is running. The engineering of open and distributed computational systems mandates for the adoption of a software infrastructure whose underlying model and technology could provide the required level of uncoupling among system components. This is the main motivation behind current research trends in the area of coordination middleware to exploit tuple-based coordination models in the engineering of complex software systems, since they intrinsically provide coordinated components with communication uncoupling and further details in the references therein. An additional daunting challenge for tuple-based models comes from knowledge-intensive application scenarios, namely, scenarios where most of the activities are based on knowledge in some form|and where knowledge becomes the prominent means by which systems get coordinated. Handling knowledge in tuple-based systems induces problems in terms of syntax - e.g., two tuples containing the same data may not match due to differences in the tuple structure - and (mostly) of semantics|e.g., two tuples representing the same information may not match based on a dierent syntax adopted. Till now, the problem has been faced by exploiting tuple-based coordination within a middleware for knowledge intensive environments: e.g., experiments with tuple-based coordination within a Semantic Web middleware (surveys analogous approaches). However, they appear to be designed to tackle the design of coordination for specic application contexts like Semantic Web and Semantic Web Services, and they result in a rather involved extension of the tuple space model. The main goal of this thesis was to conceive a more general approach to semantic coordination. In particular, it was developed the model and technology of semantic tuple centres. It is adopted the tuple centre model as main coordination abstraction to manage system interactions. A tuple centre can be seen as a programmable tuple space, i.e. an extension of a Linda tuple space, where the behaviour of the tuple space can be programmed so as to react to interaction events. By encapsulating coordination laws within coordination media, tuple centres promote coordination uncoupling among coordinated components. Then, the tuple centre model was semantically enriched: a main design choice in this work was to try not to completely redesign the existing syntactic tuple space model, but rather provide a smooth extension that { although supporting semantic reasoning { keep the simplicity of tuple and tuple matching as easier as possible. By encapsulating the semantic representation of the domain of discourse within coordination media, semantic tuple centres promote semantic uncoupling among coordinated components. The main contributions of the thesis are: (i) the design of the semantic tuple centre model; (ii) the implementation and evaluation of the model based on an existent coordination infrastructure; (iii) a view of the application scenarios in which semantic tuple centres seem to be suitable as coordination media.

Methodologies for Synthesizable Programmable Devices based on Multi-Stage Switching Networks

Nowadays the rise of non-recurring engineering (NRE) costs associated with complexity is becoming a major factor in SoC design, limiting both scaling opportunities and the flexibility advantages offered by the integration of complex computational units. The introduction of embedded programmable elements can represent an appealing solution, able both to guarantee the desired flexibility and upgradabilty and to widen the SoC market. In particular embedded FPGA (eFPGA) cores can provide bit-level optimization for those applications which benefits from synthesis, paying on the other side in terms of performance penalties and area overhead with respect to standard cell ASIC implementations. In this scenario this thesis proposes a design methodology for a synthesizable programmable device designed to be embedded in a SoC. A soft-core embedded FPGA (eFPGA) is hence presented and analyzed in terms of the opportunities given by a fully synthesizable approach, following an implementation flow based on Standard-Cell methodology. A key point of the proposed eFPGA template is that it adopts a Multi-Stage Switching Network (MSSN) as the foundation of the programmable interconnects, since it can be efficiently synthesized and optimized through a standard cell based implementation flow, ensuring at the same time an intrinsic congestion-free network topology. The evaluation of the flexibility potentialities of the eFPGA has been performed using different technology libraries (STMicroelectronics CMOS 65nm and BCD9s 0.11μm) through a design space exploration in terms of area-speed-leakage tradeoffs, enabled by the full synthesizability of the template. Since the most relevant disadvantage of the adopted soft approach, compared to a hardcore, is represented by a performance overhead increase, the eFPGA analysis has been made targeting small area budgets. The generation of the configuration bitstream has been obtained thanks to the implementation of a custom CAD flow environment, and has allowed functional verification and performance evaluation through an application-aware analysis.

Progetto e sviluppo di un banco prova per articolazioni protesiche attive ad un grado di libertà basato su programmable automation controller e motion capture

L'elaborato descrive il lavoro svolto in cinque mesi presso il Centro Protesi INAIL di Budrio (BO), che ha portato allo sviluppo di un banco prova per testare articolazioni elettromeccaniche. I dispositivi target, in particolare, sono stati due gomiti mioelettrici: il primo di produzione interna INAIL e il secondo prodotto da Selex ES in collaborazione con il Centro Protesi stesso. Per il controllo del movimento e l'acquisizione dei segnali elettrici si è scelto il PAC CompactRIO (National Instruments), mentre per le acquisizioni cinematiche di angolo e velocità angolare si è sfruttata la stereofotogrammetria.

Ottimizzazione di un'unita di controllo per protesi mioelettrica di arto superiore e confronto prestazionale tramite programmable automation controller e motion capture

Con il passare degli anni le tecnologie nel campo delle protesi mioelettriche di arto superiore stanno compiendo sempre più passi in avanti. In questo elaborato di tesi si darà un iniziale introduzione sulla protesica di arto superiore cercando di coprire tutte le possibili tipologie di protesi, prestando particolare attenzione agli arti artificiali mioelettrici. Gli scopi di questo studio sono in prima analisi una miglioria dell'unità di controllo di una protesi comandata da segnali elettromiografici di superficie, tramite l'utilizzo del nuovo IDE della Microchip (MPLAB X). In seconda analisi, invece, si attuerà un confronto prestazionale a livello di consumo in corrente di un prototipo di protesi mioelettrica nata dalla sinergia tra l'azienda "Selex ES" e il "Centro Protesi INAIL di Vigorso di Budrio". Per questo studio ci si è serviti di stereofotogrammetrica per la determinazione delle grandezze meccaniche, mentre tramite un sistema PAC si è riusciti ad ottenere specifiche grandezze elettriche. Lo studio ha portato, a livello di Firmware, l'inserimento del giusto comando di attuazione di un servofreno comandato in corrente e l'introduzione di una particolare modalità a basso consumo che consente un risparmio energetico di circa il 60% rispetto alla vecchia modalità. Discorso diverso per i risultati del confronto prestazionale che non ha portato ai risultati sperati in fase di progetto.

Programmable electronic platform for the remote control of the cell-migration galvanotaxis

Il presente lavoro di tesi nasce come collaborazione tra il Laboratorio di Progettazione Elettronica e il Laboratorio di Microscopia a Fluorescenza del Dipartimento di Fisica e Astronomia dell' Università di Bologna. In particolare nasce dalla volontà di dotare il dipartimento di un apparato sperimentale in grado di svolgere studi sulla Galvanotassia, un fenomeno biologico consistente nella migrazione di cellule sottoposte a stimolazione elettrica. La Galvanotassia è nota da fine '800 ma non sono ancora chiari i meccanismi cellulari che la provocano. Una migliore comprensione di tale fenomeno potrebbe portare importanti sviluppi in ambito medico, sia diagnostici che terapeutici. Dalla letteratura a riguardo non è emersa l'esistenza di apparecchi elettronici di controllo che permettano lo studio della Galvanotassia e che possano essere duttili a seconda del tipo di esperimento che si voglia svolgere. Da qui l'idea di iniziare lo sviluppo di un dispositivo elettronico, che fosse riprogrammabile, a basso costo e facilmente trasportabile. La progettazione di questo dispositivo ha portato ad una prima fase di test e verifiche sperimentali che hanno permesso di migliorare e affinare la costruzione di uno strumento di misura e controllo dei parametri relativi alla Galvanotassia. Sono già stati programmati test futuri che porteranno ad una versione definitiva dell' apparecchiatura alla quale succederanno più approfondite ricerche sul fenomeno della Galvanotassia.

A new approach to a model of the mammalian retina with optically programmable logic cells

This paper reports a model of the mammalian retina as well as an interpretation of some functions of the visual cortex. Its main objective is to simulate some of the behaviors observed at the different retina cells depending on the characteristics of the light impinging onto the photoreceptors. This simulation is carried out with a simple structure employed previously as basic building block of some optical computer architectures. Its possibility to perform any type of Boolean function allows a wide range of behaviors.

Synchronizing chaotic optically-programmable digital circuits

In this paper an approach to the synchronization of chaotic circuits has been reported. It is based on an optically programmable logic cell and the signals involved are fully digital. It is based on the reception of the same input signal on sender and receiver and from this approach, with a posterior correlation between both outputs, an identical chaotic output is obtained in both systems. No conversion from analog to digital signals is needed. The model here presented is based on a computer simulation.

Chaos synchronization in optically programmable logic cells

A possible approach to the synchronization of chaotic circuits is reported. It is based on an Optically Programmable Logic Cell and the signals are fully digital. A method to study the characteristics of the obtained chaos is reported as well as a new technique to compare the obtained chaos from an emitter and a receiver. This technique allows the synchronization of chaotic signals. The signals received at the receiver, composed by the addition of information and chaotic signals, are compared with the chaos generated there and a pure information signal can be detected. Its application to cryptography in Optical Communications comes directly from these properties. The model here presented is based on a computer simulation.

Optically programmable logic cells as basic units for transmission and synchronization of chaotic signals

We proposed an optical communications system, based on a digital chaotic signal where the synchronization of chaos was the main objective, in some previous papers. In this paper we will extend this work. A way to add the digital data signal to be transmitted onto the chaotic signal and its correct reception, is the main objective. We report some methods to study the main characteristics of the resulting signal. The main problem with any real system is the presence of some retard between the times than the signal is generated at the emitter at the time when this signal is received. Any system using chaotic signals as a method to encrypt need to have the same characteristics in emitter and receiver. It is because that, this control of time is needed. A method to control, in real time the chaotic signals, is reported.

Optical programmable processing element using optical fibers

The purpose of this paper is to present a new type of Optically Processing Element (OPE) based of the use of optical fibers as optical signal transmission medium.

Coder/decoder with an optical programmable logic cell

A major research area is the representation of knowledge for a given application in a compact manner such that desired information relating to this knowledge is easily recoverable. A complicated procedure may be required to recover the information from the stored representation and convert it back to usable form. Coder/decoder are the devices dedicated to that task. In this paper the capabilities that an Optical Programmable Logic Cell offers as a basic building block for coding and decoding are analyzed. We have previously published an Optically Programmable Logic Cells (OPLC), for applications as a chaotic generator or as basic element for optical computing. In optical computing previous studies these cells have been analyzed as full-adder units, being this element a basic component for the arithmetic logic structure in computing. Another application of this unit is reported in this paper. Coder and decoder are basic elements in computers, for example, in connections between processors and memory addressing. Moreover, another main application is the generation of signals for machine controlling from a certain instruction. In this paper we describe the way to obtain a coder/decoder with the OPLC and which type of applications may be the best suitable for this type of cell.

A self-timed multipurpose delay sensor for field programmable gate arrays (FPGAs)

This paper presents a novel self-timed multi-purpose sensor especially conceived for Field Programmable Gate Arrays (FPGAs). The aim of the sensor is to measure performance variations during the life-cycle of the device, such as process variability, critical path timing and temperature variations. The proposed topology, through the use of both combinational and sequential FPGA elements, amplifies the time of a signal traversing a delay chain to produce a pulse whose width is the sensor’s measurement. The sensor is fully self-timed, avoiding the need for clock distribution networks and eliminating the limitations imposed by the system clock. One single off- or on-chip time-to-digital converter is able to perform digitization of several sensors in a single operation. These features allow for a simplified approach for designers wanting to intertwine a multi-purpose sensor network with their application logic. Employed as a temperature sensor, it has been measured to have an error of ±0.67 °C, over the range of 20–100 °C, employing 20 logic elements with a 2-point calibration.