Hardware implementation of 4x4 DCT/Quantization block using multiplication and error-free algorithm

The 4ÃÂ4 discrete cosine transform is one of the most important building blocks for the emerging video coding standard, viz. H.264. The conventional implementation does some approximation to the transform matrix elements to facilitate integer arithmetic, for which hardware is suitably prepared. Though the transform coding does not involve any multiplications, quantization process requires sixteen 16-bit multiplications. The algorithm used here eliminates the process of approximation in transform coding and multiplication in the quantization process, by usage of algebraic integer coding. We propose an area-efficient implementation of the transform and quantization blocks based on the algebraic integer coding. The designs were synthesized with 90 nm TSMC CMOS technology and were also implemented on a Xilinx FPGA. The gate counts and throughput achievable in this case are 7000 and 125 Msamples/sec.

Derating Based Hardware Optimizations in Soft Error Tolerant Designs

Ensuring reliable operation over an extended period of time is one of the biggest challenges facing present day electronic systems. The increased vulnerability of the components to atmospheric particle strikes poses a big threat in attaining the reliability required for various mission critical applications. Various soft error mitigation methodologies exist to address this reliability challenge. A general solution to this problem is to arrive at a soft error mitigation methodology with an acceptable implementation overhead and error tolerance level. This implementation overhead can then be reduced by taking advantage of various derating effects like logical derating, electrical derating and timing window derating, and/or making use of application redundancy, e. g. redundancy in firmware/software executing on the so designed robust hardware. In this paper, we analyze the impact of various derating factors and show how they can be profitably employed to reduce the hardware overhead to implement a given level of soft error robustness. This analysis is performed on a set of benchmark circuits using the delayed capture methodology. Experimental results show upto 23% reduction in the hardware overhead when considering individual and combined derating factors.

Interplay of software bloat, hardware energy proportionality and system bottlenecks

In large flexible software systems, bloat occurs in many forms, causing excess resource utilization and resource bottlenecks. This results in lost throughput and wasted joules. However, mitigating bloat is not easy; efforts are best applied where savings would be substantial. To aid this we develop an analytical model establishing the relation between bottleneck in resources, bloat, performance and power. Analyses with the model places into perspective results from the first experimental study of the power-performance implications of bloat. In the experiments we find that while bloat reduction can provide as much as 40% energy savings, the degree of impact depends on hardware and software characteristics. We confirm predictions from our model with selected results from our experimental study. Our findings show that a software-only view is inadequate when assessing the effects of bloat. The impact of bloat on physical resource usage and power should be understood for a full systems perspective to properly deploy bloat reduction solutions and reap their power-performance benefits.

USHA: unified software and hardware architecture for video decoding

Video decoders used in emerging applications need to be flexible to handle a large variety of video formats and deliver scalable performance to handle wide variations in workloads. In this paper we propose a unified software and hardware architecture for video decoding to achieve scalable performance with flexibility. The light weight processor tiles and the reconfigurable hardware tiles in our architecture enable software and hardware implementations to co-exist, while a programmable interconnect enables dynamic interconnection of the tiles. Our process network oriented compilation flow achieves realization agnostic application partitioning and enables seamless migration across uniprocessor, multi-processor, semi hardware and full hardware implementations of a video decoder. An application quality of service aware scheduler monitors and controls the operation of the entire system. We prove the concept through a prototype of the architecture on an off-the-shelf FPGA. The FPGA prototype shows a scaling in performance from QCIF to 1080p resolutions in four discrete steps. We also demonstrate that the reconfiguration time is short enough to allow migration from one configuration to the other without any frame loss.

Hardware Accelerator for 3D Method of Moments based Parasitic Extraction

A Field Programmable Gate Array (FPGA) based hardware accelerator for multi-conductor parasitic capacitance extraction, using Method of Moments (MoM), is presented in this paper. Due to the prohibitive cost of solving a dense algebraic system formed by MoM, linear complexity fast solver algorithms have been developed in the past to expedite the matrix-vector product computation in a Krylov sub-space based iterative solver framework. However, as the number of conductors in a system increases leading to a corresponding increase in the number of right-hand-side (RHS) vectors, the computational cost for multiple matrix-vector products present a time bottleneck, especially for ill-conditioned system matrices. In this work, an FPGA based hardware implementation is proposed to parallelize the iterative matrix solution for multiple RHS vectors in a low-rank compression based fast solver scheme. The method is applied to accelerate electrostatic parasitic capacitance extraction of multiple conductors in a Ball Grid Array (BGA) package. Speed-ups up to 13x over equivalent software implementation on an Intel Core i5 processor for dense matrix-vector products and 12x for QR compressed matrix-vector products is achieved using a Virtex-6 XC6VLX240T FPGA on Xilinx's ML605 board.

El gráfico y las Malvinas. Periodismo deportivo en tiempos de guerra

Introducción: /.../ Uno de los acontecimientos durante el siglo pasado en los que se entremezcló la política con el deporte fue la Guerra de las Malvinas. Entre el 2 de abril y el 14 de junio de 1982, al mismo tiempo que se desarrollaban los hechos en el Atlántico Sur, el deporte argentino siguió su accionar con diferentes resultados. En medio de una feroz campaña mediática, que analizaremos más adelante, los diversos hechos deportivos que tuvieron como protagonistas a los deportistas de nuestro país se vieron reflejados en las páginas de El Gráfico. Dentro de nuestro estudio, consideramos que esa publicación no estuvo al margen de lo que sucedió en Malvinas. Nuestra hipótesis estará centrada en demostrar el apoyo editorial, como un apéndice de lo que Atlántida hizo al mismo tiempo con revistas como Gente y Somos. En resumen, la intención de la editorial en transformar al deporte y sus triunfos como una gesta épica. Y, también, la elección de héroes como vehículos de comunicación de nacionalismo.

Hardware development and ground-based studies for drop shaft experiment on oscillatory convection in half floating-zone

Coordinated measurement of temperature, velocity and free surface oscillation were obtained by using the drop shaft facility for microgravity experiments of half floating zone convection. The ground-based studies gave transition from steady to oscillatory convection for multi-quantities measurement.

Hardware basado en FPGA para síntesis de audio mediante muestras grabadas y control MIDI

El objetivo de este proyecto es desarrollar una plataforma hardware capaz de sintetizar sonidos a partir de fragmentos grabados, y de ser controlado mediante un dispositivo MIDI. Para ello se utilizará: - una placa de prototipado que incluye un dispositivo programable (FPGA) y un CODEC para la grabación/reproducción de audio digital. - un teclado MIDI.

Latt-Mayer, um estudo de caso: tecnologia na história do design gráfico brasileiro.

Nosso objetivo neste trabalho é investigar como o design gráfico se relaciona com os meios de produção da indústria gráfica brasileira. Não é comum encontrar referências abordando temas que relacionam design e tecnologia em livros sobre a história do Brasil, o que demonstra a urgência do resgate histórico de indústrias que implementaram novas tecnologias para atender a demandas projetuais e mercadológicas. Sediada na cidade do Rio de Janeiro, a clicheria Latt-Mayer como era comumente chamada, era sinônimo de qualidade e tecnologia. Entre seus clientes podemos apontar agências de publicidade, editoras, escritórios de designers e gráficas de todo país. Esta pesquisa se baseia em um corpus composto por imagens, documentos, manuais técnicos, reportagens, matrizes e depoimentos com pessoas que estiveram diretamente envolvidas com essa empresa. Catalogamos maquinaria e técnicas utilizadas, além de projetos gráficos relevantes que tiveram matrizes e provas produzidas na empresa. Por meio deste trabalho, é possível visualizar um abrangente painel histórico, que contempla um período em que ocorreram significativas transformações na relação entre designers e tecnologia na indústria gráfica brasileira.

Monteiro Lobato: editor gráfico (1918-1925)

O objetivo desta dissertação é mostrar como se deu o envolvimento de Monteiro Lobato com o design gráfico enquanto editor e gestor de suas editoras: a Edições da Revista do Brasil, a Monteiro Lobato e Cia. e a Cia. Graphico-Editora Monteiro Lobato, no período de 1918 a 1925. A análise gráfica das publicações editadas por Lobato, neste intervalo, serviu como fio condutor da pesquisa. Por fim, foi feita uma descrição gráfica dos exemplares coletados, que foram produzidos no mesmo período.