Assessing an FPGA implemented MIMO testbed with the use of channel emulator

In this paper, a channel emulator for assessing the performance of MIMO testbed implemented in a field programmable gate array technology is described. The FPGA based MIMO system includes a signal generator, modulation/demodulation and space time coding/decoding modules. The emulator uses information about a wireless channel from computer simulations or actual measurements. In simulations, a single bounce scattering model for an indoor environment is applied. The generated data is stored in the FPGA board. The tests are performed for a 2times2 MIMO system that uses Alamouti scheme for space coding/decoding. The performed tests show proper operation of the FPGA implemented MIMO testbed. Good agreement between the results using measured and simulated channel data is obtained.

Design of MIMO testbed with an FPGA board for fast signal processing

This paper describes the design of a Multiple Input Multiple Output testbed for assessing various MIMO transmission schemes in rich scattering indoor environments. In the undertaken design, a Field Programmable Gate Array (FPGA) board is used for fast processing of Intermediate Frequency signals. At the present stage, the testbed performance is assessed when the channel emulator between transmitter and receiver modules is introduced. Here, the results are presented for the case when a 2x2 Alamouti scheme for space time coding/decoding at transmitter and receiver is used. Various programming details of the FPGA board along with the obtained simulation results are reported

FPGA-based soft-core processors for image processing applications

With security and surveillance, there is an increasing need to process image data efficiently and effectively either at source or in a large data network. Whilst a Field-Programmable Gate Array (FPGA) has been seen as a key technology for enabling this, the design process has been viewed as problematic in terms of the time and effort needed for implementation and verification. The work here proposes a different approach of using optimized FPGA-based soft-core processors which allows the user to exploit the task and data level parallelism to achieve the quality of dedicated FPGA implementations whilst reducing design time. The paper also reports some preliminary
progress on the design flow to program the structure. An implementation for a Histogram of Gradients algorithm is also reported which shows that a performance of 328 fps can be achieved with this design approach, whilst avoiding the long design time, verification and debugging steps associated with conventional FPGA implementations.

Implementação em hardware reconfigurável de método de separação de dados hiperespetrais

Relatório do Trabalho Final de Mestrado para obtenção do grau de Mestre em Engenharia de Electrónica e Telecomunicações

Jännitteen reunan hallinta taajuusmuuttajissa

Diplomityössä perehdyttiin taajuusmuuttajien toimintaan ja ohjaukseen. Lisäksi työssä tarkasteltiin vaihtosuuntaajan nopeiden transienttitilojen aiheuttamaa moottorin ylijännitettä. Moottorikaapelin heijastuksia käsiteltiin vertaamalla moottorikaapelia siirtolinjaan ja todennettiin ylijännitteen syyt. Ylijännitteen vähentämiseksi on kehitetty useita suodatusmenetelmiä. Työssä vertailtiin näitä menetelmiä ja kartoitettiin kaupallisia vaihtoehtoja. Taajuusmuuttajan ohjaus on tähän päivään asti tehty yleensä käyttäen mikroprosessoria sekä logiikkapiiriä. Tulevaisuudessa ohjaukseen käytetään todennäköisesti uudelleenohjelmoitavia FPGA-piirejä (Field Programmable Gate Array). FPGA-piirin etuihin kuuluu uudelleenohjelmoitavuus sekä ohjauksen keskittäminen yhdelle piirille.

Kestomagneettitahtikoneen emulointi digitaalisella signaaliprosessorilla

Sähkökäytön suunnittelussa säätöä voidaan testata useassa tapauksessa reaaliaikasimulaattorilla todellisen laitteiston sijaan. Monet reaaliaikasimulaatioiden perustana käytetyt algoritmit soveltuvat täysinohjatulle invertterisillalle. Eräissä sovelluksissa halutaan kuitenkin käyttää puoliksiohjattua siltaa. Puoliksiohjattulla sillalla mallin kausaalisuus voi kääntyä, mitä perinteiset reaaliaikasimulaattorit eivät pysty simuloimaan Tässä työssä oli tavoitteena kehittää reaaliaikasimulaattori puoliksiohjatulle kestomagneettitahtikonekäytölle. Emulaattoriin mallinnettiin todellisen käytön kestomagneettitahtikone ja invertterisilta. Simulaattori toteutettiin digitaaliselle signaaliprosessorille (DSP) ja mittauksiin liittyvät oheislaitteet mallinnettiin FPGA-piirille. Emulaattoriin liitettiin erillinen säätäjä, jota käytettiin myös todellisen sähkökäytön säätämiseen. Emulaattorilla ja todellisella käytöllä tehtyjä mittauksia verrattiin ja emuloimalla saadut tulokset vastasivat melko hyvin todellisesta käytöstä mitattuja.

A practical method for testing high-speed networking hardware architectures

This paper deals with the key issues encountered in testing during the development of high-speed networking hardware systems by documenting a practical method for "real-life like" testing. The proposed method is empowered by modern and commonly available Field Programmable Gate Array (FPGA) technology. Innovative application of standard FPGA blocks in combination with reconfigurability are used as a back-bone of the method. A detailed elaboration of the method is given so as to serve as a general reference. The method is fully characterised and compared to alternatives through a case study proving it to be the most efficient and effective one at a reasonable cost.

A block coprocessor for user data rate improvements to GPRS coding scheme 4

The general packet radio service (GPRS) has been developed to allow packet data to be transported efficiently over an existing circuit-switched radio network, such as GSM. The main application of GPRS are in transporting Internet protocol (IP) datagrams from web servers (for telemetry or for mobile Internet browsers). Four GPRS baseband coding schemes are defined to offer a trade-off in requested data rates versus propagation channel conditions. However, data rates in the order of > 100 kbits/s are only achievable if the simplest coding scheme is used (CS-4) which offers little error detection and correction (EDC) (requiring excellent SNR) and the receiver hardware is capable of full duplex which is not currently available in the consumer market. A simple EDC scheme to improve the GPRS block error rate (BLER) performance is presented, particularly for CS-4, however gains in other coding schemes are seen. For every GPRS radio block that is corrected by the EDC scheme, the block does not need to be retransmitted releasing bandwidth in the channel and improving the user's application data rate. As GPRS requires intensive processing in the baseband, a viable field programmable gate array (FPGA) solution is presented in this paper.

Improving CS-4 user data rate in GPRS enabled devices by using a BLER co-processor

The General Packet Radio Service (GPRS) was developed to allow packet data to be transported efficiently over an existing circuit switched radio network. The main applications for GPRS are in transporting IP datagram’s from the user’s mobile Internet browser to and from the Internet, or in telemetry equipment. A simple Error Detection and Correction (EDC) scheme to improve the GPRS Block Error Rate (BLER) performance is presented, particularly for coding scheme 4 (CS-4), however gains in other coding schemes are seen. For every GPRS radio block that is corrected by the EDC scheme, the block does not need to be retransmitted releasing bandwidth in the channel, improving throughput and the user’s application data rate. As GPRS requires intensive processing in the baseband, a viable hardware solution for a GPRS BLER co-processor is discussed that has been currently implemented in a Field Programmable Gate Array (FPGA) and presented in this paper.

A Parallel Hardware Architecture for Scale and Rotation Invariant Feature Detection

This paper proposes a parallel hardware architecture for image feature detection based on the Scale Invariant Feature Transform algorithm and applied to the Simultaneous Localization And Mapping problem. The work also proposes specific hardware optimizations considered fundamental to embed such a robotic control system on-a-chip. The proposed architecture is completely stand-alone; it reads the input data directly from a CMOS image sensor and provides the results via a field-programmable gate array coupled to an embedded processor. The results may either be used directly in an on-chip application or accessed through an Ethernet connection. The system is able to detect features up to 30 frames per second (320 x 240 pixels) and has accuracy similar to a PC-based implementation. The achieved system performance is at least one order of magnitude better than a PC-based solution, a result achieved by investigating the impact of several hardware-orientated optimizations oil performance, area and accuracy.

Uma implementação da análise de componentes independentes em plataforma de hardware reconfigurável

Blind Source Separation (BSS) refers to the problem of estimate original signals from observed linear mixtures with no knowledge about the sources or the mixing process. Independent Component Analysis (ICA) is a technique mainly applied to BSS problem and from the algorithms that implement this technique, FastICA is a high performance iterative algorithm of low computacional cost that uses nongaussianity measures based on high order statistics to estimate the original sources. The great number of applications where ICA has been found useful reects the need of the implementation of this technique in hardware and the natural paralelism of FastICA favors the implementation of this algorithm on digital hardware. This work proposes the implementation of FastICA on a reconfigurable hardware platform for the viability of it's use in blind source separation problems, more specifically in a hardware prototype embedded in a Field Programmable Gate Array (FPGA) board for the monitoring of beds in hospital environments. The implementations will be carried out by Simulink models and it's synthesizing will be done through the DSP Builder software from Altera Corporation.

A novel HPF voltage source rectifier for variable speed refrigeration systems

A novel single-phase voltage source rectifier capable to achieve High-Power-Factor (HPF) for variable speed refrigeration system application, is proposed in this paper. The proposed system is composed by a single-phase high-power-factor boost rectifier, with two cells in interleave connection, operating in critical conduction mode, and employing a soft-switching technique, controlled by a Field Programmable Gate Array (FPGA), associated with a conventional three-phase IGBT bridge inverter (VSI - Voltage Source Inverter), controlled by a Digital Signal Processor (DSP). The soft-switching technique for the input stage is based on zero-current-switching (ZCS) cells. The rectifier's features include the reduction in the input current ripple, the reduction in the output voltage ripple, the use of low stress devices, low volume for the EMI input filter, high input power factor (PF), and low total harmonic distortion (THD) in the input current, in compliance with the EEC61000-3-2 standards. The digital controller for the output stage has been developed using a conventional voltage-frequency control (scalar V/f control), and a simplified stator oriented Vector control, in order to verify the feasibility and performance of the proposed digital controls for continuous temperature control applied at a refrigerator prototype.

Um novo sistema de refrigeração com controle de temperatura, compressor aberto, máquina de indução trifásica com velocidade variável e correção ativa do fator de potência do estágio de entrada

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

Retificador entrelaçado boost, no modo de condução descontínua, com técnica de correção da corrente de entrada e elevado fator de potência, para aplicação em sistema trólebus

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

Implementación de un sistema multicanal de medida de temperatura con termopares

Este proyecto fin de carrera tiene como finalidad el diseño e implementación de un sistema multicanal de medida de temperaturas con termopares con procesado digital. Se ha realizado un prototipo de cuatro canales con conexión de termopar, que es el tipo de sensor utilizado para realizar dichas medidas. La tensión generada por el termopar es procesada mediante un conversor de termopar a digital con salida en interfaz modo serie o SPI (Serial Peripheral Interface). El control de dicha comunicación se realiza por medio de un Array de Puertas Lógicas Programables o FPGA (Field Programmable Gate Array), en concreto se ha utilizado una plataforma de desarrollo modelo Virtex-5 de la empresa Xilinx. Esta tarjeta se ha programado también para el procesado software y la posterior comunicación serie con el PC, el cual consta de una interfaz de usuario donde se muestran los resultados de las medidas en tiempo real. El proyecto ha sido desarrollado en colaboración con una empresa privada dedicada principalmente al diseño electrónico. La finalidad de este prototipo es el estudio de una actualización del bloque de medida para el control de las curvas de temperatura de un equipo de reparación aeronáutica. En esta memoria se describe el proceso realizado para el desarrollo del prototipo, incluye la presentación de los estudios realizados y la información necesaria para llevar a cabo el diseño, la fabricación y la programación de los diferentes bloques que componen el sistema. ABSTRACT. The aim of this project is to implement a multichannel temperature measurement system with digital processing, using thermocouples. A four-channel prototype with thermocouple connection has been built. The thermocouple voltage is converted to digital line using a Thermocouple-to-Digital Converter with a Serial Perpheral Interface (SPI) output. The master which controls this communication is embedded in a Field Programmable Gate Array (FPGA), specifically the Xilinx Virtex-5 model. This FPGA also has the code for software temperature processing and the prototype to PC serial communication embedded. The PC user interface displays the measurement results in real time. This project has been developed at a private electronics design company. The company wants to study an update to change the analogue temperature controller equipment to a digital one. So this prototype studies a digital version of the temperature measurement block. The processes accomplished for the prototype development are detailed in the next pages of this document. It includes the studies and information needed to develop the design, manufacturing process and programming of the blocks which integrate with the global system.