Performance comparison of an active matrix flat panel imager, computed radiography system, and a screen-film system at four standard radiation qualities.

Four standard radiation qualities (from RQA 3 to RQA 9) were used to compare the imaging performance of a computed radiography (CR) system (general purpose and high resolution phosphor plates of a Kodak CR 9000 system), a selenium-based direct flat panel detector (Kodak Direct View DR 9000), and a conventional screen-film system (Kodak T-MAT L/RA film with a 3M Trimax Regular screen of speed 400) in conventional radiography. Reference exposure levels were chosen according to the manufacturer's recommendations to be representative of clinical practice (exposure index of 1700 for digital systems and a film optical density of 1.4). With the exception of the RQA 3 beam quality, the exposure levels needed to produce a mean digital signal of 1700 were higher than those needed to obtain a mean film optical density of 1.4. In spite of intense developments in the field of digital detectors, screen-film systems are still very efficient detectors for most of the beam qualities used in radiology. An important outcome of this study is the behavior of the detective quantum efficiency of the digital radiography (DR) system as a function of beam energy. The practice of users to increase beam energy when switching from a screen-film system to a CR system, in order to improve the compromise between patient dose and image quality, might not be appropriate when switching from screen-film to selenium-based DR systems.

Implementação de um Sistema MPPT em Circuito Integrado CMOS

Ao longo dos últimos anos a indústria microelectrónica tem evoluído no sentido de reduzir o consumo energético dos seus dispositivos no sentido de estes serem alimentados por fontes energéticas diversas, nomeadamente fontes renováveis. A crescente demanda por componentes energeticamente eficientes e pela miniaturização dos componentes eletrónicos exigem a conceção de fontes de alimentação com potência reduzida na ordem das dezenas de μW ás centenas de mW. Atualmente, com os crescentes avanços tecnológicos é possível obter componentes energéticamente eficientes e com tamanhos reduzidos capazes de colmatar as restrições energéticas das mais variadas aplicações. A utilização de fontes energia elétrica que tirão proveito da energia existente no meio onde se inserem os diversos dispositivos eletrónicos ou simplesmente para recarregar as baterias, apresenta-se como um dos principais objetivos a alcançar. Entre todas as energias renováveis, a energia fotovoltaica surge como umas das que proporciona um maior potencial. A sua disponibilidade global e os constantes desenvolvimentos tecnológicos no âmbito do fotovoltaico permitem o desenvolvimento de sistemas de alimentação com rendimento energético cada vez mais elevado. A presente dissertação tem como objetivo o estudo, a simulação e implementação de um conversor CC-CC, step-up, com algoritmo de controlo MPPT integrado designado por método de correlação de ripple (Ripple Correlation Control – RCC), para aplicações de baixa potência na ordem das dezenas de μW às centenas de mW. Desenvolveu-se um conversor CC-CC, autónomo, para carregamento de baterias com recurso a painéis fotovoltaicos, como fonte de energia, de forma contínua mesmo em situações de baixa luminosidade. Um circuito de gestão de energia devidamente dimensionado foi implementado com recurso a um algoritmo de procura do ponto de máxima potência (Maximum Power Point Tracking – MPPT). O objetivo desta implementação é extrair a máxima potência disponível da fonte de energia elétrica, neste caso o painel fotovoltaico, independentemente das condições meteorológicas e da potência requerida pela carga, sendo o excesso de energia redirecionado para a bateria. Nesta dissertação apresentam-se os resultados das simulações, assim como os resultados experimentais de todos os circuitos desenvolvidos de forma a validar todo o sistema implementado.

A gated single-photon avalanche diode array fabricated in a conventional CMOS process for triggered systems

A bidimensional array based on single-photon avalanche diodes for triggered imaging systems is presented. The diodes are operated in the gated mode of acquisition to reduce the probability to detect noise counts interfering with photon arrival events. In addition, low reverse bias overvoltages are used to lessen the dark count rate. Experimental results demonstrate that the prototype fabricated with a standard HV-CMOS process gets rid of afterpulses and offers a reduced dark count probability by applying the proposed modes of operation. The detector exhibits a dynamic range of 15 bits with short gated"on" periods of 10ns and a reverse bias overvoltage of 1.0V.

Avoiding sensor blindness in Geiger mode avalanche photodiode arrays fabricated in a conventional CMOS process

The need to move forward in the knowledge of the subatomic world has stimulated the development of new particle colliders. However, the objectives of the next generation of colliders sets unprecedented challenges to the detector performance. The purpose of this contribution is to present a bidimensional array based on avalanche photodiodes operated in the Geiger mode to track high energy particles in future linear colliders. The bidimensional array can function in a gated mode to reduce the probability to detect noise counts interfering with real events. Low reverse overvoltages are used to lessen the dark count rate. Experimental results demonstrate that the prototype fabricated with a standard HV-CMOS process presents an increased efficiency and avoids sensor blindness by applying the proposed techniques.

Readout schemes for low noise single-photon avalanche diodes fabricated in conventional HV-CMOS technologies

Three different pixels based on single-photon avalanche diodes for triggered applications, such as fluorescence lifetime measurements and high energy physics experiments, are presented. Each pixel consists of a 20µm x 100µm (width x length) single photon avalanche diode and a monolithically integrated readout circuit. The sensors are operated in the gated mode of acquisition to reduce the probability to detect noise counts interferring with real radiation events. Each pixel includes a different readout circuit that allows to use low reverse bias overvoltages. Experimental results demonstrate that the three pixels present a similar behaviour. The pixels get rid of afterpulses and present a reduced dark count probability by applying the gated operation. Noise figures are further improved by using low reverse bias overvoltages. The detectors exhibit an input dynamic range of 13.35 bits with short gated"on" periods of 10ns and a reverse bias overvoltage of 0.5V. The three pixels have been fabricated in a standard HV-CMOS process.

Readout electronics for low dark count pixel detectors based on geiger mode avalanche photodiodes fabricated in conventional CMOS technologies for future linear colliders

The high sensitivity and excellent timing accuracy of Geiger mode avalanche photodiodes makes them ideal sensors as pixel detectors for particle tracking in high energy physics experiments to be performed in future linear colliders. Nevertheless, it is well known that these sensors suffer from dark counts and afterpulsing noise, which induce false hits (indistinguishable from event detection) as well as an increase of the necessary area of the readout system. In this work, we present a comparison between APDs fabricated in a high voltage 0.35 µm and a high integration 0.13 µm commercially available CMOS technologies that has been performed to determine which of them best fits the particle collider requirements. In addition, a readout circuit that allows low noise operation is introduced. Experimental characterization of the proposed pixel is also presented in this work.

Low dark count geiger mode avalanche photodiodes fabricated in conventional CMOS technologies

Avalanche photodiodes operated in the Geiger mode present very high intrinsic gain and fast time response, which make the sensor an ideal option for those applications in which detectors with high sensitivity and velocity are required. Moreover, they are compatible with conventional CMOS technologies, allowing sensor and front-end electronics integration within the pixel cell. Despite these excellent qualities, the photodiode suffers from high intrinsic noise, which degrades the performance of the detector and increases the memory area to store the total amount of information generated. In this work, a new front-end circuit that allows low reverse bias overvoltage sensor operation to reduce the noise in Geiger mode avalanche photodiode pixel detectors is presented. The proposed front-end circuit also enables to operate the sensor in the gated acquisition mode to further reduce the noise. Experimental characterization of the fabricated pixel with the conventional HV-AMS 0.35µm technology is also presented in this article.

Potential and Challenges of Analog Reconfigurable Computation in Modern and Future CMOS

In this work, the feasibility of the floating-gate technology in analog computing platforms in a scaled down general-purpose CMOS technology is considered. When the technology is scaled down the performance of analog circuits tends to get worse because the process parameters are optimized for digital transistors and the scaling involves the reduction of supply voltages. Generally, the challenge in analog circuit design is that all salient design metrics such as power, area, bandwidth and accuracy are interrelated. Furthermore, poor flexibility, i.e. lack of reconfigurability, the reuse of IP etc., can be considered the most severe weakness of analog hardware. On this account, digital calibration schemes are often required for improved performance or yield enhancement, whereas high flexibility/reconfigurability can not be easily achieved. Here, it is discussed whether it is possible to work around these obstacles by using floating-gate transistors (FGTs), and analyze problems associated with the practical implementation. FGT technology is attractive because it is electrically programmable and also features a charge-based built-in non-volatile memory. Apart from being ideal for canceling the circuit non-idealities due to process variations, the FGTs can also be used as computational or adaptive elements in analog circuits. The nominal gate oxide thickness in the deep sub-micron (DSM) processes is too thin to support robust charge retention and consequently the FGT becomes leaky. In principle, non-leaky FGTs can be implemented in a scaled down process without any special masks by using “double”-oxide transistors intended for providing devices that operate with higher supply voltages than general purpose devices. However, in practice the technology scaling poses several challenges which are addressed in this thesis. To provide a sufficiently wide-ranging survey, six prototype chips with varying complexity were implemented in four different DSM process nodes and investigated from this perspective. The focus is on non-leaky FGTs, but the presented autozeroing floating-gate amplifier (AFGA) demonstrates that leaky FGTs may also find a use. The simplest test structures contain only a few transistors, whereas the most complex experimental chip is an implementation of a spiking neural network (SNN) which comprises thousands of active and passive devices. More precisely, it is a fully connected (256 FGT synapses) two-layer spiking neural network (SNN), where the adaptive properties of FGT are taken advantage of. A compact realization of Spike Timing Dependent Plasticity (STDP) within the SNN is one of the key contributions of this thesis. Finally, the considerations in this thesis extend beyond CMOS to emerging nanodevices. To this end, one promising emerging nanoscale circuit element - memristor - is reviewed and its applicability for analog processing is considered. Furthermore, it is discussed how the FGT technology can be used to prototype computation paradigms compatible with these emerging two-terminal nanoscale devices in a mature and widely available CMOS technology.

A Comaparison Study of EM and Physical Equivalent Circuit Modeling for MIM CMOS Capacitors

In this Letter a new physical model for metal-insulatormetal CMOS capacitors is presented. In the model the parameters of the circuit are derived from the physical structural details. Physical behaviors due to metal skin effect and inductance have been considered. The model has been confirmed by 3D EM simulator and design rules proposed. The model presented is scalable with capacitor geometry, allowing designers to predict and optimize quality factor. The approach has been verified for MIM CMOS capacitors

Equipos didácticos multimedia para la enseñanza de las famílias lógicas : pmos, nmos y cmos.

En el día a día del aula universitaria, se ha hecho necesario el uso de diferente material de apoyo a la docencia. Para el estudio en profundidad de la familia Mos, se ha desarrollado un libro teórico y uno de los complementos con unos programas tutores de elaboración propia que ofrecen al estudiante un nuevo punto de vista basaso en la interactividad para ayudar a comprenderlos y sirviéndose, al mismo tiempo, de tutoría y autoevaluación.

Cooled Infrared Dichroic Beamsplitters and Filters for the MIRI Spectrometer and Imager (5-29µm)

The spectral design and fabrication of cooled (7K) mid-infrared dichroic beamsplitters and bandpass filter coatings for the MIRI spectrometer and imager are described. Design methods to achieve the spectral performance and coating materials are discussed.

The radial width of a coronal mass ejection between 0.1 and 0.4 AU estimated from the heliospheric imager on STEREO

On 15-17 February 2008, a CME with an approximately circular cross section was tracked through successive images obtained by the Heliospheric Imager (HI) instrument onboard the STEREO-A spacecraft. Reasoning that an idealised flux rope is cylindrical in shape with a circular cross-section, best fit circles are used to determine the radial width of the CME. As part of the process the radial velocity and longitude of propagation are determined by fits to elongation-time maps as 252±5 km/s and 70±5° respectively. With the longitude known, the radial size is calculated from the images, taking projection effects into account. The radial width of the CME, S (AU), obeys a power law with heliocentric distance, R, as the CME travels between 0.1 and 0.4 AU, such that S=0.26 R0.6±0.1. The exponent value obtained is compared to published studies based on statistical surveys of in situ spacecraft observations of ICMEs between 0.3 and 1.0 AU, and general agreement is found. This paper demonstrates the new opportunities provided by HI to track the radial width of CMEs through the previously unobservable zone between the LASCO field of view and Helios in situ measurements.

Topographic and thermal mapping of volcanic terrain using AVTIS ground-based 94-GHz dual-mode radar/radiometric imager

The All-Weather Volcano Topography Imaging Sensor remote sensing instrument is a custom-built millimeter-wave (MMW) sensor that has been developed as a practical field tool for remote sensing of volcanic terrain at active lava domes. The portable instrument combines active and passive MMW measurements to record topographic and thermal data in almost all weather conditions from ground-based survey points. We describe how the instrument is deployed in the field, the quality of the primary ranging and radiometric measurements, and the postprocessing techniques used to derive the geophysical products of the target terrain, surface temperature, and reflectivity. By comparison of changing topography, we estimate the volume change and the lava extrusion rate. Validation of the MMW radiometry is also presented by quantitative comparison with coincident infrared thermal imagery.