Pela Estrada Larga : Fernando Fernandes e a memória duma geração de livreiros

História da Livraria Leitura do Porto e a Divulgação Cultural.

Diseño del proceso de devolución automática del impuesto a la renta a personas naturales en relación de dependencia en el Ecuador

A través de este trabajo de investigación se pretende diseñar un proceso de devolución automática de los saldos a favor de Impuesto a la Renta de personas naturales en relación de dependencia, sin la necesidad de que el contribuyente presente una petición o reclamo de los valores pagados en exceso o indebidamente; esta propuesta pretende que la Administración Tributaria pueda brindar nuevas alternativas para la devolución de saldos a favor de Impuesto a la Renta, realizando controles previos y que la devolución de los valores no constituyan un riesgo para la Administración. Se hace necesario en primera instancia una evaluación de la normativa legal y los procedimientos actuales que regulan la devolución de Impuesto a la Renta y en función de llevar a cabo esta propuesta es necesaria la utilización y aplicación de conceptos de reingeniería de procesos que permitirán mejoras sustanciales en la atención de este tipo de devoluciones. Con el desarrollo de esta propuesta se pretende mejorar, ampliar, integrar y validar la información que se obtiene de los contribuyentes y de sus agentes de retención; disminuir los costos directos e indirectos en los que la Administración Tributaria incurre para poder responder la atención de las solicitudes de pago indebido y en exceso de Impuesto a la Renta; y a su vez permitirá brindar a los contribuyentes un servicio más eficiente.

A practical method for testing high-speed networking hardware architectures

This paper deals with the key issues encountered in testing during the development of high-speed networking hardware systems by documenting a practical method for "real-life like" testing. The proposed method is empowered by modern and commonly available Field Programmable Gate Array (FPGA) technology. Innovative application of standard FPGA blocks in combination with reconfigurability are used as a back-bone of the method. A detailed elaboration of the method is given so as to serve as a general reference. The method is fully characterised and compared to alternatives through a case study proving it to be the most efficient and effective one at a reasonable cost.

A compositional framework for hardware/software co-design

We describe a compositional framework, together with its supporting toolset, for hardware/software co-design. Our framework is an integration of a formal approach within a traditional design flow. The formal approach is based on Interval Temporal Logic and its executable subset, Tempura. Refinement is the key element in our framework because it will derive from a single formal specification of the system the software and hardware parts of the implementation, while preserving all properties of the system specification. During refinement simulation is used to choose the appropriate refinement rules, which are applied automatically in the HOL system. The framework is illustrated with two case studies. The work presented is part of a UK collaborative research project between the Software Technology Research Laboratory at the De Montfort University and the Oxford University Computing Laboratory.

Hardware development of the Yorick series of active vision systems

This paper presents a review of the design and development of the Yorick series of active stereo camera platforms and their integration into real-time closed loop active vision systems, whose applications span surveillance, navigation of autonomously guided vehicles (AGVs), and inspection tasks for teleoperation, including immersive visual telepresence. The mechatronic approach adopted for the design of the first system, including head/eye platform, local controller, vision engine, gaze controller and system integration, proved to be very successful. The design team comprised researchers with experience in parallel computing, robot control, mechanical design and machine vision. The success of the project has generated sufficient interest to sanction a number of revisions of the original head design, including the design of a lightweight compact head for use on a robot arm, and the further development of a robot head to look specifically at increasing visual resolution for visual telepresence. The controller and vision processing engines have also been upgraded, to include the control of robot heads on mobile platforms and control of vergence through tracking of an operator's eye movement. This paper details the hardware development of the different active vision/telepresence systems.

A specific pole placement technique to minimise hardware requirements within a real time terrestrial and cable video echo canceller

The real time hardware architecture of a deterministic video echo canceller (deghoster) system is presented. The deghoster is capable of calculating all the multipath channel distortion characteristics from terrestrial and cable television in one single pass while performing real time video in-line ghost cancellation. The results from the actual system are also presented in this paper.

A compact low-cost electronic hardware design for actuating soft robots

A low cost, compact embedded design approach for actuating soft robots is presented. The complete fabrication procedure and mode of operation was demonstrated, and the performance of the complete system was also demonstrated by building a microcontroller based hardware system which was used to actuate a soft robot for bending motion. The actuation system including the electronic circuit board and actuation components was embedded in a 3D-printed casing to ensure a compact approach for actuating soft robots. Results show the viability of the system in actuating and controlling siliconebased soft robots to achieve bending motions. Qualitative measurements of uniaxial tensile test, bending distance and pressure were obtained. This electronic design is easy to reproduce and integrate into any specified soft robotic device requiring pneumatic actuation.

A Parallel Hardware Architecture for Scale and Rotation Invariant Feature Detection

This paper proposes a parallel hardware architecture for image feature detection based on the Scale Invariant Feature Transform algorithm and applied to the Simultaneous Localization And Mapping problem. The work also proposes specific hardware optimizations considered fundamental to embed such a robotic control system on-a-chip. The proposed architecture is completely stand-alone; it reads the input data directly from a CMOS image sensor and provides the results via a field-programmable gate array coupled to an embedded processor. The results may either be used directly in an on-chip application or accessed through an Ethernet connection. The system is able to detect features up to 30 frames per second (320 x 240 pixels) and has accuracy similar to a PC-based implementation. The achieved system performance is at least one order of magnitude better than a PC-based solution, a result achieved by investigating the impact of several hardware-orientated optimizations oil performance, area and accuracy.

O comprometimento organizacional da geração Y no setor de conhecimento intenso

Dissertação apresentada ao Programa de Pós- Graduação em Administração – Mestrado da Universidade Municipal de São Caetano do Sul, como requisito parcial para a obtenção do título de Mestre em Administração.

Análise do processo de geração de conhecimento para inivação tecnolôgica em instituições de pesquisa agripecuária

Tese apresentada ao Programa de Pós-graduação em Administração da Universidade Municipal de São Caetano do Sul.