Safety and exercise tolerance of acute high altitude exposure (3454 m) among patients with coronary artery disease

OBJECTIVES: To assess the safety and cardiopulmonary adaptation to high altitude exposure among patients with coronary artery disease. METHODS: 22 patients (20 men and 2 women), mean age 57 (SD 7) years, underwent a maximal, symptom limited exercise stress test in Bern, Switzerland (540 m) and after a rapid ascent to the Jungfraujoch (3454 m). The study population comprised 15 patients after ST elevation myocardial infarction and 7 after a non-ST elevation myocardial infarction 12 (SD 4) months after the acute event. All patients were revascularised either by percutaneous coronary angioplasty (n = 15) or by coronary artery bypass surgery (n = 7). Ejection fraction was 60 (SD 8)%. beta blocking agents were withheld for five days before exercise testing. RESULTS: At 3454 m, peak oxygen uptake decreased by 19% (p < 0.001), maximum work capacity by 15% (p < 0.001) and exercise time by 16% (p < 0.001); heart rate, ventilation and lactate were significantly higher at every level of exercise, except at maximum exertion. No ECG signs of myocardial ischaemia or significant arrhythmias were noted. CONCLUSIONS: Although oxygen demand and lactate concentrations are higher during exercise at high altitude, a rapid ascent and submaximal exercise can be considered safe at an altitude of 3454 m for low risk patients six months after revascularisation for an acute coronary event and a normal exercise stress test at low altitude.

Survey of shift and work tolerance of City of Houston emergency medical service personnel

This study of ambulance workers for the emergency medical services of the City of Houston studied the factors related to shiftwork tolerance and intolerance. The EMS personnel work a 24-hour shift with rotating days of the week. Workers are assigned to A, B, C, D shift, each of which rotate 24-hours on, 24-hours off, 24-hours on and 4 days off. One-hundred and seventy-six male EMTs, paramedics and chauffeurs from stations of varying levels of activity were surveyed. The sample group ranged in age from 20 to 45. The average tenure on the job was 8.2 years. Over 68% of the workers held a second job, the majority of which worked over 20 hours a week at the second position.^ The survey instrument was a 20-page questionnaire modeled after the Folkard Standardized Shiftwork Index. In addition to demographic data, the survey tool provided measurements of general job satisfaction, sleep quality, general health complaints, morningness/eveningness, cognitive and somatic anxiety, depression, and circadian types. The survey questionnaire included an EMS-specific scaler of stress.^ A conceptual model of Shiftwork Tolerance was presented to identify the key factors examined in the study. An extensive list of 265 variables was reduced to 36 key variables that related to: (1) shift schedule and demographic/lifestyle factors, (2) individual differences related to traits and characteristics, and (3) tolerance/intolerance effects. Using the general job satisfaction scaler as the key measurement of shift tolerance/intolerance, it was shown that a significant relationship existed between this dependent variable and stress, number of years working a 24-hour shift, sleep quality, languidness/vigorousness. The usual amount of sleep received during the shift, general health complaints and flexibility/rigidity (R$\sp2$ =.5073).^ The sample consisted of a majority of morningness-types or extreme-morningness types, few evening-types and no extreme-evening types, duplicating the findings of Motohashi's previous study of ambulance workers. The level of activity by station was not significant on any of the dependent variables examined. However, the shift worked had a relationship with sleep quality, despite the fact that all shifts work the same hours and participate in the same rotation schedule. ^

Inhibition of glutathione synthesis reduces chilling tolerance in maize

The role of glutathione (GSH) in protecting plants from chilling injury was analyzed in seedlings of a chilling-tolerant maize (Zea mays L.) genotype using buthionine sulfoximine (BSO), a specific inhibitor of gamma-glutamylcysteine (gamma EC) synthetase, the first enzyme of GSH synthesis. At 25 degrees C, 1 mM BSO significantly increased cysteine and reduced GSH content and GSH reductase (GR: EC 1.6.4.2) activity, but interestingly affected neither fresh weight nor dry weight nor relative injury. Application of BSO up to 1 mM during chilling at 5 degrees C reduced the fresh and dry weights of shoots and roots and increased relative injury from 10 to almost 40%. Buthionine sulfoximine also induced a decrease in GR activity of 90 and 40% in roots and shoots, respectively. Addition of GSH or gamma EC together with BSO to the nutrient solution protected the seedlings from the BSO effect by increasing the levels of GSH and GR activity in roots and shoots. During chilling, the level of abscisic acid increased both in controls and BSO-treated seedlings and decreased after chilling in roots and shoots of the controls and in the roots of BSO-treated seedlings, but increased in their shoots. Taken together, our results show that BSO did not reduce chilling tolerance of the maize genotype analyzed by inhibiting abscisic acid accumulation but by establishing a low level of GSH. which also induced a decrease in GR activity.

Development and improvement of protection-system algorithms for ground-fault detection and location in synchronous machines

Uno de los defectos más frecuentes en los generadores síncronos son los defectos a tierra tanto en el devanado estatórico, como de excitación. Se produce un defecto cuando el aislamiento eléctrico entre las partes activas de cualquiera de estos devanados y tierra se reduce considerablemente o desaparece. La detección de los defectos a tierra en ambos devanados es un tema ampliamente estudiado a nivel industrial. Tras la detección y confirmación de la existencia del defecto, dicha falta debe ser localizada a lo largo del devanado para su reparación, para lo que habitualmente el rotor debe ser extraído del estator. Esta operación resulta especialmente compleja y cara. Además, el hecho de limitar la corriente de defecto en ambos devanados provoca que el defecto no sea localizable visualmente, pues apenas existe daño en el generador. Por ello, se deben aplicar técnicas muy laboriosas para localizar exactamente el defecto y poder así reparar el devanado. De cara a reducir el tiempo de reparación, y con ello el tiempo en que el generador esta fuera de servicio, cualquier información por parte del relé de protección acerca de la localización del defecto resultaría de gran utilidad. El principal objetivo de esta tesis doctoral ha sido el desarrollo de nuevos algoritmos que permitan la estimación de la localización de los defectos a tierra tanto en el devanado rotórico como estatórico de máquinas síncronas. Respecto al devanado de excitación, se ha presentado un nuevo método de localización de defectos a tierra para generadores con excitación estática. Este método permite incluso distinguir si el defecto se ha producido en el devanado de excitación, o en cualquiera de los componentes del sistema de excitación, esto es, transformador de excitación, conductores de alimentación del rectificador controlado, etc. En caso de defecto a tierra en del devanado rotórico, este método proporciona una estimación de su localización. Sin embargo, para poder obtener la localización del defecto, se precisa conocer el valor de resistencia de defecto. Por ello, en este trabajo se presenta además un nuevo método para la estimación de este parámetro de forma precisa. Finalmente, se presenta un nuevo método de detección de defectos a tierra, basado en el criterio direccional, que complementa el método de localización, permitiendo tener en cuenta la influencia de las capacidades a tierra del sistema. Estas capacidades resultan determinantes a la hora de localizar el defecto de forma adecuada. En relación con el devanado estatórico, en esta tesis doctoral se presenta un nuevo algoritmo de localización de defectos a tierra para generadores que dispongan de la protección de faltas a tierra basada en la inyección de baja frecuencia. Se ha propuesto un método general, que tiene en cuenta todos los parámetros del sistema, así como una versión simplificada del método para generadores con capacidades a tierra muy reducida, que podría resultar de fácil implementación en relés de protección comercial. Los algoritmos y métodos presentados se han validado mediante ensayos experimentales en un generador de laboratorio de 5 kVA, así como en un generador comercial de 106 MVA con resultados satisfactorios y prometedores. ABSTRACT One of the most common faults in synchronous generators is the ground fault in both the stator winding and the excitation winding. In case of fault, the insulation level between the active part of any of these windings and ground lowers considerably, or even disappears. The detection of ground faults in both windings is a very researched topic. The fault current is typically limited intentionally to a reduced level. This allows to detect easily the ground faults, and therefore to avoid damage in the generator. After the detection and confirmation of the existence of a ground fault, it should be located along the winding in order to repair of the machine. Then, the rotor has to be extracted, which is a very complex and expensive operation. Moreover, the fact of limiting the fault current makes that the insulation failure is not visually detectable, because there is no visible damage in the generator. Therefore, some laborious techniques have to apply to locate accurately the fault. In order to reduce the repair time, and therefore the time that the generator is out of service, any information about the approximate location of the fault would be very useful. The main objective of this doctoral thesis has been the development of new algorithms and methods to estimate the location of ground faults in the stator and in the rotor winding of synchronous generators. Regarding the excitation winding, a new location method of ground faults in excitation winding of synchronous machines with static excitation has been presented. This method allows even to detect if the fault is at the excitation winding, or in any other component of the excitation system: controlled rectifier, excitation transformer, etc. In case of ground fault in the rotor winding, this method provides an estimation of the fault location. However, in order to calculate the location, the value of fault resistance is necessary. Therefore, a new fault-resistance estimation algorithm is presented in this text. Finally, a new fault detection algorithm based on directional criterion is described to complement the fault location method. This algorithm takes into account the influence of the capacitance-to-ground of the system, which has a remarkable impact in the accuracy of the fault location. Regarding the stator winding, a new fault-location algorithm has been presented for stator winding of synchronous generators. This algorithm is applicable to generators with ground-fault protection based in low-frequency injection. A general algorithm, which takes every parameter of the system into account, has been presented. Moreover, a simplified version of the algorithm has been proposed for generators with especially low value of capacitance to ground. This simplified algorithm might be easily implementable in protective relays. The proposed methods and algorithms have been tested in a 5 kVA laboratory generator, as well as in a 106 MVA synchronous generator with satisfactory and promising results.

Optimizing the reliability and resource efficiency of MapReduce-based systems

Debido al gran incremento de datos digitales que ha tenido lugar en los últimos años, ha surgido un nuevo paradigma de computación paralela para el procesamiento eficiente de grandes volúmenes de datos. Muchos de los sistemas basados en este paradigma, también llamados sistemas de computación intensiva de datos, siguen el modelo de programación de Google MapReduce. La principal ventaja de los sistemas MapReduce es que se basan en la idea de enviar la computación donde residen los datos, tratando de proporcionar escalabilidad y eficiencia. En escenarios libres de fallo, estos sistemas generalmente logran buenos resultados. Sin embargo, la mayoría de escenarios donde se utilizan, se caracterizan por la existencia de fallos. Por tanto, estas plataformas suelen incorporar características de tolerancia a fallos y fiabilidad. Por otro lado, es reconocido que las mejoras en confiabilidad vienen asociadas a costes adicionales en recursos. Esto es razonable y los proveedores que ofrecen este tipo de infraestructuras son conscientes de ello. No obstante, no todos los enfoques proporcionan la misma solución de compromiso entre las capacidades de tolerancia a fallo (o de manera general, las capacidades de fiabilidad) y su coste. Esta tesis ha tratado la problemática de la coexistencia entre fiabilidad y eficiencia de los recursos en los sistemas basados en el paradigma MapReduce, a través de metodologías que introducen el mínimo coste, garantizando un nivel adecuado de fiabilidad. Para lograr esto, se ha propuesto: (i) la formalización de una abstracción de detección de fallos; (ii) una solución alternativa a los puntos únicos de fallo de estas plataformas, y, finalmente, (iii) un nuevo sistema de asignación de recursos basado en retroalimentación a nivel de contenedores. Estas contribuciones genéricas han sido evaluadas tomando como referencia la arquitectura Hadoop YARN, que, hoy en día, es la plataforma de referencia en la comunidad de los sistemas de computación intensiva de datos. En la tesis se demuestra cómo todas las contribuciones de la misma superan a Hadoop YARN tanto en fiabilidad como en eficiencia de los recursos utilizados. ABSTRACT Due to the increase of huge data volumes, a new parallel computing paradigm to process big data in an efficient way has arisen. Many of these systems, called dataintensive computing systems, follow the Google MapReduce programming model. The main advantage of these systems is based on the idea of sending the computation where the data resides, trying to provide scalability and efficiency. In failure-free scenarios, these frameworks usually achieve good results. However, these ones are not realistic scenarios. Consequently, these frameworks exhibit some fault tolerance and dependability techniques as built-in features. On the other hand, dependability improvements are known to imply additional resource costs. This is reasonable and providers offering these infrastructures are aware of this. Nevertheless, not all the approaches provide the same tradeoff between fault tolerant capabilities (or more generally, reliability capabilities) and cost. In this thesis, we have addressed the coexistence between reliability and resource efficiency in MapReduce-based systems, looking for methodologies that introduce the minimal cost and guarantee an appropriate level of reliability. In order to achieve this, we have proposed: (i) a formalization of a failure detector abstraction; (ii) an alternative solution to single points of failure of these frameworks, and finally (iii) a novel feedback-based resource allocation system at the container level. Finally, our generic contributions have been instantiated for the Hadoop YARN architecture, which is the state-of-the-art framework in the data-intensive computing systems community nowadays. The thesis demonstrates how all our approaches outperform Hadoop YARN in terms of reliability and resource efficiency.

Parametric and structural self-adaptation of embedded systems using evolvable hardware

Los sistemas empotrados han sido concebidos tradicionalmente como sistemas de procesamiento específicos que realizan una tarea fija durante toda su vida útil. Para cumplir con requisitos estrictos de coste, tamaño y peso, el equipo de diseño debe optimizar su funcionamiento para condiciones muy específicas. Sin embargo, la demanda de mayor versatilidad, un funcionamiento más inteligente y, en definitiva, una mayor capacidad de procesamiento comenzaron a chocar con estas limitaciones, agravado por la incertidumbre asociada a entornos de operación cada vez más dinámicos donde comenzaban a ser desplegados progresivamente. Esto trajo como resultado una necesidad creciente de que los sistemas pudieran responder por si solos a eventos inesperados en tiempo diseño tales como: cambios en las características de los datos de entrada y el entorno del sistema en general; cambios en la propia plataforma de cómputo, por ejemplo debido a fallos o defectos de fabricación; y cambios en las propias especificaciones funcionales causados por unos objetivos del sistema dinámicos y cambiantes. Como consecuencia, la complejidad del sistema aumenta, pero a cambio se habilita progresivamente una capacidad de adaptación autónoma sin intervención humana a lo largo de la vida útil, permitiendo que tomen sus propias decisiones en tiempo de ejecución. Éstos sistemas se conocen, en general, como sistemas auto-adaptativos y tienen, entre otras características, las de auto-configuración, auto-optimización y auto-reparación. Típicamente, la parte soft de un sistema es mayoritariamente la única utilizada para proporcionar algunas capacidades de adaptación a un sistema. Sin embargo, la proporción rendimiento/potencia en dispositivos software como microprocesadores en muchas ocasiones no es adecuada para sistemas empotrados. En este escenario, el aumento resultante en la complejidad de las aplicaciones está siendo abordado parcialmente mediante un aumento en la complejidad de los dispositivos en forma de multi/many-cores; pero desafortunadamente, esto hace que el consumo de potencia también aumente. Además, la mejora en metodologías de diseño no ha sido acorde como para poder utilizar toda la capacidad de cómputo disponible proporcionada por los núcleos. Por todo ello, no se están satisfaciendo adecuadamente las demandas de cómputo que imponen las nuevas aplicaciones. La solución tradicional para mejorar la proporción rendimiento/potencia ha sido el cambio a unas especificaciones hardware, principalmente usando ASICs. Sin embargo, los costes de un ASIC son altamente prohibitivos excepto en algunos casos de producción en masa y además la naturaleza estática de su estructura complica la solución a las necesidades de adaptación. Los avances en tecnologías de fabricación han hecho que la FPGA, una vez lenta y pequeña, usada como glue logic en sistemas mayores, haya crecido hasta convertirse en un dispositivo de cómputo reconfigurable de gran potencia, con una cantidad enorme de recursos lógicos computacionales y cores hardware empotrados de procesamiento de señal y de propósito general. Sus capacidades de reconfiguración han permitido combinar la flexibilidad propia del software con el rendimiento del procesamiento en hardware, lo que tiene la potencialidad de provocar un cambio de paradigma en arquitectura de computadores, pues el hardware no puede ya ser considerado más como estático. El motivo es que como en el caso de las FPGAs basadas en tecnología SRAM, la reconfiguración parcial dinámica (DPR, Dynamic Partial Reconfiguration) es posible. Esto significa que se puede modificar (reconfigurar) un subconjunto de los recursos computacionales en tiempo de ejecución mientras el resto permanecen activos. Además, este proceso de reconfiguración puede ser ejecutado internamente por el propio dispositivo. El avance tecnológico en dispositivos hardware reconfigurables se encuentra recogido bajo el campo conocido como Computación Reconfigurable (RC, Reconfigurable Computing). Uno de los campos de aplicación más exóticos y menos convencionales que ha posibilitado la computación reconfigurable es el conocido como Hardware Evolutivo (EHW, Evolvable Hardware), en el cual se encuentra enmarcada esta tesis. La idea principal del concepto consiste en convertir hardware que es adaptable a través de reconfiguración en una entidad evolutiva sujeta a las fuerzas de un proceso evolutivo inspirado en el de las especies biológicas naturales, que guía la dirección del cambio. Es una aplicación más del campo de la Computación Evolutiva (EC, Evolutionary Computation), que comprende una serie de algoritmos de optimización global conocidos como Algoritmos Evolutivos (EA, Evolutionary Algorithms), y que son considerados como algoritmos universales de resolución de problemas. En analogía al proceso biológico de la evolución, en el hardware evolutivo el sujeto de la evolución es una población de circuitos que intenta adaptarse a su entorno mediante una adecuación progresiva generación tras generación. Los individuos pasan a ser configuraciones de circuitos en forma de bitstreams caracterizados por descripciones de circuitos reconfigurables. Seleccionando aquellos que se comportan mejor, es decir, que tienen una mejor adecuación (o fitness) después de ser evaluados, y usándolos como padres de la siguiente generación, el algoritmo evolutivo crea una nueva población hija usando operadores genéticos como la mutación y la recombinación. Según se van sucediendo generaciones, se espera que la población en conjunto se aproxime a la solución óptima al problema de encontrar una configuración del circuito adecuada que satisfaga las especificaciones. El estado de la tecnología de reconfiguración después de que la familia de FPGAs XC6200 de Xilinx fuera retirada y reemplazada por las familias Virtex a finales de los 90, supuso un gran obstáculo para el avance en hardware evolutivo; formatos de bitstream cerrados (no conocidos públicamente); dependencia de herramientas del fabricante con soporte limitado de DPR; una velocidad de reconfiguración lenta; y el hecho de que modificaciones aleatorias del bitstream pudieran resultar peligrosas para la integridad del dispositivo, son algunas de estas razones. Sin embargo, una propuesta a principios de los años 2000 permitió mantener la investigación en el campo mientras la tecnología de DPR continuaba madurando, el Circuito Virtual Reconfigurable (VRC, Virtual Reconfigurable Circuit). En esencia, un VRC en una FPGA es una capa virtual que actúa como un circuito reconfigurable de aplicación específica sobre la estructura nativa de la FPGA que reduce la complejidad del proceso reconfiguración y aumenta su velocidad (comparada con la reconfiguración nativa). Es un array de nodos computacionales especificados usando descripciones HDL estándar que define recursos reconfigurables ad-hoc: multiplexores de rutado y un conjunto de elementos de procesamiento configurables, cada uno de los cuales tiene implementadas todas las funciones requeridas, que pueden seleccionarse a través de multiplexores tal y como ocurre en una ALU de un microprocesador. Un registro grande actúa como memoria de configuración, por lo que la reconfiguración del VRC es muy rápida ya que tan sólo implica la escritura de este registro, el cual controla las señales de selección del conjunto de multiplexores. Sin embargo, esta capa virtual provoca: un incremento de área debido a la implementación simultánea de cada función en cada nodo del array más los multiplexores y un aumento del retardo debido a los multiplexores, reduciendo la frecuencia de funcionamiento máxima. La naturaleza del hardware evolutivo, capaz de optimizar su propio comportamiento computacional, le convierten en un buen candidato para avanzar en la investigación sobre sistemas auto-adaptativos. Combinar un sustrato de cómputo auto-reconfigurable capaz de ser modificado dinámicamente en tiempo de ejecución con un algoritmo empotrado que proporcione una dirección de cambio, puede ayudar a satisfacer los requisitos de adaptación autónoma de sistemas empotrados basados en FPGA. La propuesta principal de esta tesis está por tanto dirigida a contribuir a la auto-adaptación del hardware de procesamiento de sistemas empotrados basados en FPGA mediante hardware evolutivo. Esto se ha abordado considerando que el comportamiento computacional de un sistema puede ser modificado cambiando cualquiera de sus dos partes constitutivas: una estructura hard subyacente y un conjunto de parámetros soft. De esta distinción, se derivan dos lineas de trabajo. Por un lado, auto-adaptación paramétrica, y por otro auto-adaptación estructural. El objetivo perseguido en el caso de la auto-adaptación paramétrica es la implementación de técnicas de optimización evolutiva complejas en sistemas empotrados con recursos limitados para la adaptación paramétrica online de circuitos de procesamiento de señal. La aplicación seleccionada como prueba de concepto es la optimización para tipos muy específicos de imágenes de los coeficientes de los filtros de transformadas wavelet discretas (DWT, DiscreteWavelet Transform), orientada a la compresión de imágenes. Por tanto, el objetivo requerido de la evolución es una compresión adaptativa y más eficiente comparada con los procedimientos estándar. El principal reto radica en reducir la necesidad de recursos de supercomputación para el proceso de optimización propuesto en trabajos previos, de modo que se adecúe para la ejecución en sistemas empotrados. En cuanto a la auto-adaptación estructural, el objetivo de la tesis es la implementación de circuitos auto-adaptativos en sistemas evolutivos basados en FPGA mediante un uso eficiente de sus capacidades de reconfiguración nativas. En este caso, la prueba de concepto es la evolución de tareas de procesamiento de imagen tales como el filtrado de tipos desconocidos y cambiantes de ruido y la detección de bordes en la imagen. En general, el objetivo es la evolución en tiempo de ejecución de tareas de procesamiento de imagen desconocidas en tiempo de diseño (dentro de un cierto grado de complejidad). En este caso, el objetivo de la propuesta es la incorporación de DPR en EHW para evolucionar la arquitectura de un array sistólico adaptable mediante reconfiguración cuya capacidad de evolución no había sido estudiada previamente. Para conseguir los dos objetivos mencionados, esta tesis propone originalmente una plataforma evolutiva que integra un motor de adaptación (AE, Adaptation Engine), un motor de reconfiguración (RE, Reconfiguration Engine) y un motor computacional (CE, Computing Engine) adaptable. El el caso de adaptación paramétrica, la plataforma propuesta está caracterizada por: • un CE caracterizado por un núcleo de procesamiento hardware de DWT adaptable mediante registros reconfigurables que contienen los coeficientes de los filtros wavelet • un algoritmo evolutivo como AE que busca filtros wavelet candidatos a través de un proceso de optimización paramétrica desarrollado específicamente para sistemas caracterizados por recursos de procesamiento limitados • un nuevo operador de mutación simplificado para el algoritmo evolutivo utilizado, que junto con un mecanismo de evaluación rápida de filtros wavelet candidatos derivado de la literatura actual, asegura la viabilidad de la búsqueda evolutiva asociada a la adaptación de wavelets. En el caso de adaptación estructural, la plataforma propuesta toma la forma de: • un CE basado en una plantilla de array sistólico reconfigurable de 2 dimensiones compuesto de nodos de procesamiento reconfigurables • un algoritmo evolutivo como AE que busca configuraciones candidatas del array usando un conjunto de funcionalidades de procesamiento para los nodos disponible en una biblioteca accesible en tiempo de ejecución • un RE hardware que explota la capacidad de reconfiguración nativa de las FPGAs haciendo un uso eficiente de los recursos reconfigurables del dispositivo para cambiar el comportamiento del CE en tiempo de ejecución • una biblioteca de elementos de procesamiento reconfigurables caracterizada por bitstreams parciales independientes de la posición, usados como el conjunto de configuraciones disponibles para los nodos de procesamiento del array Las contribuciones principales de esta tesis se pueden resumir en la siguiente lista: • Una plataforma evolutiva basada en FPGA para la auto-adaptación paramétrica y estructural de sistemas empotrados compuesta por un motor computacional (CE), un motor de adaptación (AE) evolutivo y un motor de reconfiguración (RE). Esta plataforma se ha desarrollado y particularizado para los casos de auto-adaptación paramétrica y estructural. • En cuanto a la auto-adaptación paramétrica, las contribuciones principales son: – Un motor computacional adaptable mediante registros que permite la adaptación paramétrica de los coeficientes de una implementación hardware adaptativa de un núcleo de DWT. – Un motor de adaptación basado en un algoritmo evolutivo desarrollado específicamente para optimización numérica, aplicada a los coeficientes de filtros wavelet en sistemas empotrados con recursos limitados. – Un núcleo IP de DWT auto-adaptativo en tiempo de ejecución para sistemas empotrados que permite la optimización online del rendimiento de la transformada para compresión de imágenes en entornos específicos de despliegue, caracterizados por tipos diferentes de señal de entrada. – Un modelo software y una implementación hardware de una herramienta para la construcción evolutiva automática de transformadas wavelet específicas. • Por último, en cuanto a la auto-adaptación estructural, las contribuciones principales son: – Un motor computacional adaptable mediante reconfiguración nativa de FPGAs caracterizado por una plantilla de array sistólico en dos dimensiones de nodos de procesamiento reconfigurables. Es posible mapear diferentes tareas de cómputo en el array usando una biblioteca de elementos sencillos de procesamiento reconfigurables. – Definición de una biblioteca de elementos de procesamiento apropiada para la síntesis autónoma en tiempo de ejecución de diferentes tareas de procesamiento de imagen. – Incorporación eficiente de la reconfiguración parcial dinámica (DPR) en sistemas de hardware evolutivo, superando los principales inconvenientes de propuestas previas como los circuitos reconfigurables virtuales (VRCs). En este trabajo también se comparan originalmente los detalles de implementación de ambas propuestas. – Una plataforma tolerante a fallos, auto-curativa, que permite la recuperación funcional online en entornos peligrosos. La plataforma ha sido caracterizada desde una perspectiva de tolerancia a fallos: se proponen modelos de fallo a nivel de CLB y de elemento de procesamiento, y usando el motor de reconfiguración, se hace un análisis sistemático de fallos para un fallo en cada elemento de procesamiento y para dos fallos acumulados. – Una plataforma con calidad de filtrado dinámica que permite la adaptación online a tipos de ruido diferentes y diferentes comportamientos computacionales teniendo en cuenta los recursos de procesamiento disponibles. Por un lado, se evolucionan filtros con comportamientos no destructivos, que permiten esquemas de filtrado en cascada escalables; y por otro, también se evolucionan filtros escalables teniendo en cuenta requisitos computacionales de filtrado cambiantes dinámicamente. Este documento está organizado en cuatro partes y nueve capítulos. La primera parte contiene el capítulo 1, una introducción y motivación sobre este trabajo de tesis. A continuación, el marco de referencia en el que se enmarca esta tesis se analiza en la segunda parte: el capítulo 2 contiene una introducción a los conceptos de auto-adaptación y computación autonómica (autonomic computing) como un campo de investigación más general que el muy específico de este trabajo; el capítulo 3 introduce la computación evolutiva como la técnica para dirigir la adaptación; el capítulo 4 analiza las plataformas de computación reconfigurables como la tecnología para albergar hardware auto-adaptativo; y finalmente, el capítulo 5 define, clasifica y hace un sondeo del campo del hardware evolutivo. Seguidamente, la tercera parte de este trabajo contiene la propuesta, desarrollo y resultados obtenidos: mientras que el capítulo 6 contiene una declaración de los objetivos de la tesis y la descripción de la propuesta en su conjunto, los capítulos 7 y 8 abordan la auto-adaptación paramétrica y estructural, respectivamente. Finalmente, el capítulo 9 de la parte 4 concluye el trabajo y describe caminos de investigación futuros. ABSTRACT Embedded systems have traditionally been conceived to be specific-purpose computers with one, fixed computational task for their whole lifetime. Stringent requirements in terms of cost, size and weight forced designers to highly optimise their operation for very specific conditions. However, demands for versatility, more intelligent behaviour and, in summary, an increased computing capability began to clash with these limitations, intensified by the uncertainty associated to the more dynamic operating environments where they were progressively being deployed. This brought as a result an increasing need for systems to respond by themselves to unexpected events at design time, such as: changes in input data characteristics and system environment in general; changes in the computing platform itself, e.g., due to faults and fabrication defects; and changes in functional specifications caused by dynamically changing system objectives. As a consequence, systems complexity is increasing, but in turn, autonomous lifetime adaptation without human intervention is being progressively enabled, allowing them to take their own decisions at run-time. This type of systems is known, in general, as selfadaptive, and are able, among others, of self-configuration, self-optimisation and self-repair. Traditionally, the soft part of a system has mostly been so far the only place to provide systems with some degree of adaptation capabilities. However, the performance to power ratios of software driven devices like microprocessors are not adequate for embedded systems in many situations. In this scenario, the resulting rise in applications complexity is being partly addressed by rising devices complexity in the form of multi and many core devices; but sadly, this keeps on increasing power consumption. Besides, design methodologies have not been improved accordingly to completely leverage the available computational power from all these cores. Altogether, these factors make that the computing demands new applications pose are not being wholly satisfied. The traditional solution to improve performance to power ratios has been the switch to hardware driven specifications, mainly using ASICs. However, their costs are highly prohibitive except for some mass production cases and besidesthe static nature of its structure complicates the solution to the adaptation needs. The advancements in fabrication technologies have made that the once slow, small FPGA used as glue logic in bigger systems, had grown to be a very powerful, reconfigurable computing device with a vast amount of computational logic resources and embedded, hardened signal and general purpose processing cores. Its reconfiguration capabilities have enabled software-like flexibility to be combined with hardware-like computing performance, which has the potential to cause a paradigm shift in computer architecture since hardware cannot be considered as static anymore. This is so, since, as is the case with SRAMbased FPGAs, Dynamic Partial Reconfiguration (DPR) is possible. This means that subsets of the FPGA computational resources can now be changed (reconfigured) at run-time while the rest remains active. Besides, this reconfiguration process can be triggered internally by the device itself. This technological boost in reconfigurable hardware devices is actually covered under the field known as Reconfigurable Computing. One of the most exotic fields of application that Reconfigurable Computing has enabled is the known as Evolvable Hardware (EHW), in which this dissertation is framed. The main idea behind the concept is turning hardware that is adaptable through reconfiguration into an evolvable entity subject to the forces of an evolutionary process, inspired by that of natural, biological species, that guides the direction of change. It is yet another application of the field of Evolutionary Computation (EC), which comprises a set of global optimisation algorithms known as Evolutionary Algorithms (EAs), considered as universal problem solvers. In analogy to the biological process of evolution, in EHW the subject of evolution is a population of circuits that tries to get adapted to its surrounding environment by progressively getting better fitted to it generation after generation. Individuals become circuit configurations representing bitstreams that feature reconfigurable circuit descriptions. By selecting those that behave better, i.e., with a higher fitness value after being evaluated, and using them as parents of the following generation, the EA creates a new offspring population by using so called genetic operators like mutation and recombination. As generations succeed one another, the whole population is expected to approach to the optimum solution to the problem of finding an adequate circuit configuration that fulfils system objectives. The state of reconfiguration technology after Xilinx XC6200 FPGA family was discontinued and replaced by Virtex families in the late 90s, was a major obstacle for advancements in EHW; closed (non publicly known) bitstream formats; dependence on manufacturer tools with highly limiting support of DPR; slow speed of reconfiguration; and random bitstream modifications being potentially hazardous for device integrity, are some of these reasons. However, a proposal in the first 2000s allowed to keep investigating in this field while DPR technology kept maturing, the Virtual Reconfigurable Circuit (VRC). In essence, a VRC in an FPGA is a virtual layer acting as an application specific reconfigurable circuit on top of an FPGA fabric that reduces the complexity of the reconfiguration process and increases its speed (compared to native reconfiguration). It is an array of computational nodes specified using standard HDL descriptions that define ad-hoc reconfigurable resources; routing multiplexers and a set of configurable processing elements, each one containing all the required functions, which are selectable through functionality multiplexers as in microprocessor ALUs. A large register acts as configuration memory, so VRC reconfiguration is very fast given it only involves writing this register, which drives the selection signals of the set of multiplexers. However, large overheads are introduced by this virtual layer; an area overhead due to the simultaneous implementation of every function in every node of the array plus the multiplexers, and a delay overhead due to the multiplexers, which also reduces maximum frequency of operation. The very nature of Evolvable Hardware, able to optimise its own computational behaviour, makes it a good candidate to advance research in self-adaptive systems. Combining a selfreconfigurable computing substrate able to be dynamically changed at run-time with an embedded algorithm that provides a direction for change, can help fulfilling requirements for autonomous lifetime adaptation of FPGA-based embedded systems. The main proposal of this thesis is hence directed to contribute to autonomous self-adaptation of the underlying computational hardware of FPGA-based embedded systems by means of Evolvable Hardware. This is tackled by considering that the computational behaviour of a system can be modified by changing any of its two constituent parts: an underlying hard structure and a set of soft parameters. Two main lines of work derive from this distinction. On one side, parametric self-adaptation and, on the other side, structural self-adaptation. The goal pursued in the case of parametric self-adaptation is the implementation of complex evolutionary optimisation techniques in resource constrained embedded systems for online parameter adaptation of signal processing circuits. The application selected as proof of concept is the optimisation of Discrete Wavelet Transforms (DWT) filters coefficients for very specific types of images, oriented to image compression. Hence, adaptive and improved compression efficiency, as compared to standard techniques, is the required goal of evolution. The main quest lies in reducing the supercomputing resources reported in previous works for the optimisation process in order to make it suitable for embedded systems. Regarding structural self-adaptation, the thesis goal is the implementation of self-adaptive circuits in FPGA-based evolvable systems through an efficient use of native reconfiguration capabilities. In this case, evolution of image processing tasks such as filtering of unknown and changing types of noise and edge detection are the selected proofs of concept. In general, evolving unknown image processing behaviours (within a certain complexity range) at design time is the required goal. In this case, the mission of the proposal is the incorporation of DPR in EHW to evolve a systolic array architecture adaptable through reconfiguration whose evolvability had not been previously checked. In order to achieve the two stated goals, this thesis originally proposes an evolvable platform that integrates an Adaptation Engine (AE), a Reconfiguration Engine (RE) and an adaptable Computing Engine (CE). In the case of parametric adaptation, the proposed platform is characterised by: • a CE featuring a DWT hardware processing core adaptable through reconfigurable registers that holds wavelet filters coefficients • an evolutionary algorithm as AE that searches for candidate wavelet filters through a parametric optimisation process specifically developed for systems featured by scarce computing resources • a new, simplified mutation operator for the selected EA, that together with a fast evaluation mechanism of candidate wavelet filters derived from existing literature, assures the feasibility of the evolutionary search involved in wavelets adaptation In the case of structural adaptation, the platform proposal takes the form of: • a CE based on a reconfigurable 2D systolic array template composed of reconfigurable processing nodes • an evolutionary algorithm as AE that searches for candidate configurations of the array using a set of computational functionalities for the nodes available in a run time accessible library • a hardware RE that exploits native DPR capabilities of FPGAs and makes an efficient use of the available reconfigurable resources of the device to change the behaviour of the CE at run time • a library of reconfigurable processing elements featured by position-independent partial bitstreams used as the set of available configurations for the processing nodes of the array Main contributions of this thesis can be summarised in the following list. • An FPGA-based evolvable platform for parametric and structural self-adaptation of embedded systems composed of a Computing Engine, an evolutionary Adaptation Engine and a Reconfiguration Engine. This platform is further developed and tailored for both parametric and structural self-adaptation. • Regarding parametric self-adaptation, main contributions are: – A CE adaptable through reconfigurable registers that enables parametric adaptation of the coefficients of an adaptive hardware implementation of a DWT core. – An AE based on an Evolutionary Algorithm specifically developed for numerical optimisation applied to wavelet filter coefficients in resource constrained embedded systems. – A run-time self-adaptive DWT IP core for embedded systems that allows for online optimisation of transform performance for image compression for specific deployment environments characterised by different types of input signals. – A software model and hardware implementation of a tool for the automatic, evolutionary construction of custom wavelet transforms. • Lastly, regarding structural self-adaptation, main contributions are: – A CE adaptable through native FPGA fabric reconfiguration featured by a two dimensional systolic array template of reconfigurable processing nodes. Different processing behaviours can be automatically mapped in the array by using a library of simple reconfigurable processing elements. – Definition of a library of such processing elements suited for autonomous runtime synthesis of different image processing tasks. – Efficient incorporation of DPR in EHW systems, overcoming main drawbacks from the previous approach of virtual reconfigurable circuits. Implementation details for both approaches are also originally compared in this work. – A fault tolerant, self-healing platform that enables online functional recovery in hazardous environments. The platform has been characterised from a fault tolerance perspective: fault models at FPGA CLB level and processing elements level are proposed, and using the RE, a systematic fault analysis for one fault in every processing element and for two accumulated faults is done. – A dynamic filtering quality platform that permits on-line adaptation to different types of noise and different computing behaviours considering the available computing resources. On one side, non-destructive filters are evolved, enabling scalable cascaded filtering schemes; and on the other, size-scalable filters are also evolved considering dynamically changing computational filtering requirements. This dissertation is organized in four parts and nine chapters. First part contains chapter 1, the introduction to and motivation of this PhD work. Following, the reference framework in which this dissertation is framed is analysed in the second part: chapter 2 features an introduction to the notions of self-adaptation and autonomic computing as a more general research field to the very specific one of this work; chapter 3 introduces evolutionary computation as the technique to drive adaptation; chapter 4 analyses platforms for reconfigurable computing as the technology to hold self-adaptive hardware; and finally chapter 5 defines, classifies and surveys the field of Evolvable Hardware. Third part of the work follows, which contains the proposal, development and results obtained: while chapter 6 contains an statement of the thesis goals and the description of the proposal as a whole, chapters 7 and 8 address parametric and structural self-adaptation, respectively. Finally, chapter 9 in part 4 concludes the work and describes future research paths.

Cellular mechanisms of neuropathic pain, morphine tolerance, and their interactions

Compelling evidence has accumulated over the last several years from our laboratory, as well as others, indicating that central hyperactive states resulting from neuronal plastic changes within the spinal cord play a critical role in hyperalgesia associated with nerve injury and inflammation. In our laboratory, chronic constriction injury of the common sciatic nerve, a rat model of neuropathic pain, has been shown to result in activation of central nervous system excitatory amino acid receptors and subsequent intracellular cascades including protein kinase C translocation and activation, nitric oxide production, and nitric oxide-activated poly(ADP ribose) synthetase activation. Similar cellular mechanisms also have been implicated in the development of tolerance to the analgesic effects of morphine. A recently observed phenomenon, the development of “dark neurons,” is associated with both chronic constriction injury and morphine tolerance. A site of action involved in both hyperalgesia and morphine tolerance is in the superficial laminae of the spinal cord dorsal horn. These observations suggest that hyperalgesia and morphine tolerance may be interrelated at the level of the superficial laminae of the dorsal horn by common neural substrates that interact at the level of excitatory amino acid receptor activation and subsequent intracellular events. The demonstration of interrelationships between neural mechanisms underlying hyperalgesia and morphine tolerance may lead to a better understanding of the neurobiology of these two phenomena in particular and pain in general. This knowledge may also provide a scientific basis for improved pain management with opiate analgesics.

Tolerance of human MSH2+/− lymphoblastoid cells to the methylating agent temozolomide

Members of hereditary nonpolyposis colon cancer (HNPCC) families harboring heterozygous germline mutations in the DNA mismatch repair genes hMSH2 or hMLH1 present with tumors generally two to three decades earlier than individuals with nonfamilial sporadic colon cancer. We searched for phenotypic features that might predispose heterozygous cells from HNPCC kindreds to malignant transformation. hMSH2+/− lymphoblastoid cell lines were found to be on average about 4-fold more tolerant than wild-type cells to killing by the methylating agent temozolomide, a phenotype that is invariably linked with impairment of the mismatch repair system. This finding was associated with an average 2-fold decrease of the steady-state level of hMSH2 protein in hMSH2+/− cell lines. In contrast, hMLH1+/− heterozygous cells were indistinguishable from normal controls in these assays. Thus, despite the fact that HNPCC families harboring mutations in hMSH2 or hMLH1 cannot be distinguished clinically, the early stages of the carcinogenic process in hMSH2 and hMLH1 mutation carriers may be different. Should hMSH2+/− colonocytes and lymphoblasts harbor a similar phenotype, the increased tolerance of the former to DNA-damaging agents present in the human colon may play a key role in the initiation of the carcinogenic process.

Evidence for the Critical Role of Sucrose Synthase for Anoxic Tolerance of Maize Roots using a Double Mutant

The induction of the sucrose synthase (SuSy) gene (SuSy) by low O2, low temperature, and limiting carbohydrate supply suggested a role in carbohydrate metabolism under stress conditions. The isolation of a maize (Zea mays L.) line mutant for the two known SuSy genes but functionally normal showed that SuSy activity might not be required for aerobic growth and allowed the possibility of investigating its importance during anaerobic stress. As assessed by root elongation after return to air, hypoxic pretreatment improved anoxic tolerance, in correlation with the number of SuSy genes and the level of SuSy expression. Furthermore, root death in double-mutant seedlings during anoxic incubation could be attributed to the impaired utilization of sucrose (Suc). Collectively, these data provide unequivocal evidence that Suc is the principal C source and that SuSy is the main enzyme active in Suc breakdown in roots of maize seedlings deprived of O2. In this situation, SuSy plays a critical role in anoxic tolerance.

A design pattern for efficient retrieval of large data sets from remote data sources

Retrieving large amounts of information over wide area networks, including the Internet, is problematic due to issues arising from latency of response, lack of direct memory access to data serving resources, and fault tolerance. This paper describes a design pattern for solving the issues of handling results from queries that return large amounts of data. Typically these queries would be made by a client process across a wide area network (or Internet), with one or more middle-tiers, to a relational database residing on a remote server. The solution involves implementing a combination of data retrieval strategies, including the use of iterators for traversing data sets and providing an appropriate level of abstraction to the client, double-buffering of data subsets, multi-threaded data retrieval, and query slicing. This design has recently been implemented and incorporated into the framework of a commercial software product developed at Oracle Corporation.

Design of a modular, high step-up ratio DC–DC converter for HVDC applications integrating offshore wind power

High-power and high-voltage gain dc-dc converters are key to high-voltage direct current (HVDC) power transmission for offshore wind power. This paper presents an isolated ultra-high step-up dc-dc converter in matrix transformer configuration. A flyback-forward converter is adopted as the power cell and the secondary side matrix connection is introduced to increase the power level and to improve fault tolerance. Because of the modular structure of the converter, the stress on the switching devices is decreased and so is the transformer size. The proposed topology can be operated in column interleaved modes, row interleaved modes, and hybrid working modes in order to deal with the varying energy from the wind farm. Furthermore, fault-tolerant operation is also realized in several fault scenarios. A 400-W dc-dc converter with four cells is developed and experimentally tested to validate the proposed technique, which can be applied to high-power high-voltage dc power transmission.

Hardware Implementation of a Fault-Tolerant Hopfield Neural Network on FPGAs

This letter presents an FPGA implementation of a fault-tolerant Hopfield NeuralNetwork (HNN). The robustness of this circuit against Single Event Upsets (SEUs) and Single Event Transients (SETs) has been evaluated. Results show the fault tolerance of the proposed design, compared to a previous non fault- tolerant implementation and a solution based on triple modular redundancy (TMR) of a standard HNN design.

Application-Based Analysis of Register File Criticality for Reliability Assessment in Embedded Microprocessors

There is an increasing concern to reduce the cost and overheads during the development of reliable systems. Selective protection of most critical parts of the systems represents a viable solution to obtain a high level of reliability at a fraction of the cost. In particular to design a selective fault mitigation strategy for processor-based systems, it is mandatory to identify and prioritize the most vulnerable registers in the register file as best candidates to be protected (hardened). This paper presents an application-based metric to estimate the criticality of each register from the microprocessor register file in microprocessor-based systems. The proposed metric relies on the combination of three different criteria based on common features of executed applications. The applicability and accuracy of our proposal have been evaluated in a set of applications running in different microprocessors. Results show a significant improvement in accuracy compared to previous approaches and regardless of the underlying architecture.

Comparação entre métodos para mensuração da potência aeróbia em atletas tetraplégicos= : Comparison of methods for aerobic power assessment in athletes with tetraplegia

Universidade Estadual de Campinas . Faculdade de Educação Física

Collagen V-induced nasal tolerance downregulates pulmonary collagen mRNA gene and TGF-beta expression in experimental systemic sclerosis

Background: The purpose of this study was to evaluate collagen deposition, mRNA collagen synthesis and TGFbeta expression in the lung tissue in an experimental model of scleroderma after collagen V-induced nasal tolerance. Methods: Female New Zealand rabbits (N = 12) were immunized with 1 mg/ml of collagen V in Freund's adjuvant (IM). After 150 days, six immunized animals were tolerated by nasal administration of collagen V ( 25 mu g/day) (IM-TOL) daily for 60 days. The collagen content was determined by morphometry, and mRNA expressions of types I, III and V collagen were determined by Real-time PCR. The TGF-beta expression was evaluated by immunostaining and quantified by point counting methods. To statistic analysis ANOVA with Bonferroni test were employed for multiple comparison when appropriate and the level of significance was determined to be p < 0.05. Results: IM-TOL, when compared to IM, showed significant reduction in total collagen content around the vessels (0.371 +/- 0.118 vs. 0.874 +/- 0.282, p < 0.001), bronchioles (0.294 +/- 0.139 vs. 0.646 +/- 0.172, p < 0.001) and in the septal interstitium (0.027 +/- 0.014 vs. 0.067 +/- 0.039, p = 0.026). The lung tissue of IM-TOL, when compared to IM, showed decreased immunostaining of types I, III and V collagen, reduced mRNA expression of types I (0.10 +/- 0.07 vs. 1.0 +/- 0.528, p = 0.002) and V (1.12 +/- 0.42 vs. 4.74 +/- 2.25, p = 0.009) collagen, in addition to decreased TGF-beta expression ( p < 0.0001). Conclusions: Collagen V-induced nasal tolerance in the experimental model of SSc regulated the pulmonary remodeling process, inhibiting collagen deposition and collagen I and V mRNA synthesis. Additionally, it decreased TGF-beta expression, suggesting a promising therapeutic option for scleroderma treatment.