Hardware Accelerator for 3D Method of Moments based Parasitic Extraction

A Field Programmable Gate Array (FPGA) based hardware accelerator for multi-conductor parasitic capacitance extraction, using Method of Moments (MoM), is presented in this paper. Due to the prohibitive cost of solving a dense algebraic system formed by MoM, linear complexity fast solver algorithms have been developed in the past to expedite the matrix-vector product computation in a Krylov sub-space based iterative solver framework. However, as the number of conductors in a system increases leading to a corresponding increase in the number of right-hand-side (RHS) vectors, the computational cost for multiple matrix-vector products present a time bottleneck, especially for ill-conditioned system matrices. In this work, an FPGA based hardware implementation is proposed to parallelize the iterative matrix solution for multiple RHS vectors in a low-rank compression based fast solver scheme. The method is applied to accelerate electrostatic parasitic capacitance extraction of multiple conductors in a Ball Grid Array (BGA) package. Speed-ups up to 13x over equivalent software implementation on an Intel Core i5 processor for dense matrix-vector products and 12x for QR compressed matrix-vector products is achieved using a Virtex-6 XC6VLX240T FPGA on Xilinx's ML605 board.

A Time-based Low Voltage Body Temperature Monitoring Unit

A neonatal temperature monitoring system operating in subthreshold regime that utilizes time mode signal processing is presented. Resistance deviations in a thermistor due to temperature variations are converted to delay variations that are subsequently quantized by a Delay measurement unit (DMU). The DMU does away with the need for any analog circuitry and is synthesizable entirely from digital logic. An FPGA implementation of the system demonstrates the viability of employing time mode signal processing, and measured results show that temperature resolution better than 0.1 degrees C can be achieved using this approach.

A Gold Sensors Array for Imaging The Real Tissue Phantom in Electrical Impedance Tomography

Surface electrodes in Electrical Impedance Tomography (EIT) phantoms usually reduce the SNR of the boundary potential data due to their design and development errors. A novel gold sensors array with high geometric precision is developed for EIT phantoms to improve the resistivity image quality. Gold thin films are deposited on a flexible FR4 sheet using electro-deposition process to make a sixteen electrode array with electrodes of identical geometry. A real tissue gold electrode phantom is developed with chicken tissue paste and the fat cylinders as the inhomogeneity. Boundary data are collected using a USB based high speed data acquisition system in a LabVIEW platform for different inhomogeneity positions. Resistivity images are reconstructed using EIDORS and compared with identical stainless steel electrode systems. Image contrast parameters are calculated from the resistivity matrix and the reconstructed images are evaluated for both the phantoms. Image contrast and image resolution of resistivity images are improved with gold electrode array.

Desarrollo de estándares y estrategias para el establecimiento de un archivo vivo del patrimonio digital alavés

[ES] Como parte de este proyecto de investigación se realizó el siguiente proyecto fin de carrera:

Aprendizaje basado en proyectos en Diseño y Construcción de Sistemas Digitales

Duración (en horas): Más de 50 horas. Destinatario: Estudiante y Docente

Enriching the content provided by cultural catalogues with data from institutional repositories

[EN] This paper is an outcome of the ERASMUS IP program called TOPCART, there are more information about this project that can be accessed from the following item:

Circuitos integrados reconfigurables de bajo consumo

El objetivo principal del trabajo es el diseño, utilizando técnicas de bajo consumo, del algoritmo de cifrado estándar AES (Advanced Encryption Standard) y su implementación sobre dispositivos reconfigurables, en particular sobre una FPGA.

Elektrokadiografo baten diseinu eta eraikuntza

Sistemen Informatikan Ingeniaritza Teknikoa (S.I.I.T.) karrerako amaierako proiektu honetan “ELEKTROKADIOGRAFO BATEN DISEINU ETA ERAIKUNTZA” aztertzen da. Sarrera gisa proiektuaren nondik-norakoak eta honen helburuak azalduko dira. Bigarren atalean elektrokardiograma (EKG), bere historia eta berarekin zuzenki lotuta dagoen elektrokardiografoa aztertzen dira. Bihotzaren aktibitate elektrikoak, EKG-rekin duen erlazioa azaltzen da eta azken honen atal desberdinak nola interpretatzen diren bihotzeko hainbat gaixotasunen diagnosia egiteko. Hirugarren atalean elektrokardiografoaren diseinu eta inplementazioa garatuko da lau azpiataletan banatuta. Lehenbizikoa, seinale bioelektrikoa eskuratzeko beharrezkoa den zirkuitu analogikoari dagokio. Bigarrena, seinalea mikrokontrolagailu baten bidez digitalizatu eta konputagailura USB bidez transmititzeko beharrezko zirkuitu digitala eta bere firmwareari. Hirugarrena, mikrokontrolagailutik datuak lortzeko Windows eta Linuxerako softwareari eta azkenik web aplikazio bati, gordetako datuak tratatu eta internet bidez aztertu ahal izateko. Ondorioetan lortutako emaitzak aztertuko dira eta elektrokardiografoaren diseinu eta inplementazioa hobetzeko proposamenak egingo dira. Bibliografian proiektua egiteko erabili diren web orrialde eta softwarera estekak zerrendatzen dira. Proiektuan lagundu didaten pertsona guztiei eskerrik beroenak, beraien laguntzarik gabe ezinezkoa izango baitzen hau aurrera eramatea. Azkenik eranskinetan CD bat atxikitzen da non garatu diren aplikazio guztiak, beraien iturburu kodea eta lortutako emaitzen datu fitxategiak dauden.

Design, analysis and implementation of a versatile low level radio frequency system for accelerating cavities

179 p.

Kontrol esparruan ikasketa eta garapenerako oinarrizko ingurune praktiko, ireki eta askea

Embedded system design (VHDL description) based on Xilinx's Spartan3E Development Kit to perform real-time PID control and monitoring of DC motors.

Adaptive Scalable SVD Unit for Fast Processing of Large LSE Problems

Singular Value Decomposition (SVD) is a key linear algebraic operation in many scientific and engineering applications. In particular, many computational intelligence systems rely on machine learning methods involving high dimensionality datasets that have to be fast processed for real-time adaptability. In this paper we describe a practical FPGA (Field Programmable Gate Array) implementation of a SVD processor for accelerating the solution of large LSE problems. The design approach has been comprehensive, from the algorithmic refinement to the numerical analysis to the customization for an efficient hardware realization. The processing scheme rests on an adaptive vector rotation evaluator for error regularization that enhances convergence speed with no penalty on the solution accuracy. The proposed architecture, which follows a data transfer scheme, is scalable and based on the interconnection of simple rotations units, which allows for a trade-off between occupied area and processing acceleration in the final implementation. This permits the SVD processor to be implemented both on low-cost and highend FPGAs, according to the final application requirements.

Observational and theoretical advances in cosmological foreground emission

Observational and theoretical work towards the separation of foreground emission from the cosmic microwave background is described. The bulk of this work is in the design, construction, and commissioning of the C-Band All-Sky Survey (C-BASS), an experiment to produce a template of the Milky Way Galaxy's polarized synchrotron emission. Theoretical work is the derivation of an analytical approximation to the emission spectrum of spinning dust grains.

The performance of the C-BASS experiment is demonstrated through a preliminary, deep survey of the North Celestial Pole region. A comparison to multiwavelength data is performed, and the thermal and systematic noise properties of the experiment are explored. The systematic noise has been minimized through careful data processing algorithms, implemented both in the experiment's Field Programmable Gate Array (FPGA) based digital backend and in the data analysis pipeline. Detailed descriptions of these algorithms are presented.

The analytical function of spinning dust emission is derived through the application of careful approximations, with each step tested against numerical calculations. This work is intended for use in the parameterized separation of cosmological foreground components and as a framework for interpreting and comparing the variety of anomalous microwave emission observations.

Reloj basado en señales GPS con corrección digital para PTP-Master

[ES]este proyecto trata sobre el desarrollo de un core en una FPGA para conseguir, gracias a un módulo GPS, una referencia temporal precisa, necesaria para un equipo PTP master (IEEE-1588), a bajo coste y con calidad Grand Master.

Cargador fotovoltaico para Smartphones de última generación.

[ES]Este proyecto tiene como objetivo diseñar e implementar un prototipo de un cargador fotovoltaico para teléfonos móviles de última generación. Dicho prototipo constará de un panel fotovoltaico, reguladores de tensión y corriente, un MPPT, un regulador de carga de batería, una batería auxiliar y una conexión USB para conectarlo al dispositivo a cargar. Para su realización, se llevará a cabo un estudio previo para obtener conocimientos sobre el funcionamiento de las nuevas tecnologías en esta área, su oferta en el mercado, y se hará uso de las herramientas necesarias para su diseño, implementación y pruebas posteriores.

Reloj basado en señales GPS con corrección por tensión para PTP-Master

[ES]El proyecto presentado a continuación muestra la elaboración de un core para ser embebido dentro de las denominadas FPGAs (Field Programmable Gate Array), cuya finalidad es la creación de una referencia temporal, en arquitectura de 64bits, gracias a un módulo GPS (Global Positioning System), lo más cercana posible al orden de las decenas de nano-segundos, para poder ser insertado en un equipo PTP-Master (Precision Time Protocol - Master) (IEEE (Institute of Electrical and Electronics Engineers) - 1588), a bajo coste y con calidad comparable a la de los dispositivos Grand Master.