Optimisation of source/drain extension region profile for suppression of short channel effects in sub-50 nm DG SOI MOSFETs with high- k gate dielectrics

Novel technology dependent scaling parameters i.e. spacer to gradient ratio and effective channel length (Leff) are proposed for source/drain engineered DG MOSFET, and their significance in minimizing short channel effects (SCES) in high-k gate dielectrics is discussed in detail. Results show that a high-k dielectric should be associated with a higher spacer to gradient ratio to minimise SCEs The analytical model agrees with simulated data over the entire range of spacer widths, doping gradients, high-k gate dielectrics and effective channel lengths.

Performance assessment of nanoscale double- and triple- gate FinFETs

This is the first paper to describe performance assessment of triple and double gate FinFETs for High Performance (HP), Low Operating Power (LOP) and Low Standby Power (LSTP) logic technologies is investigated. The impact of gate work-function, spacer width, lateral source/drain doping gradient, fin aspect ratio, fin thickness on device performance, has been analysed in detail and guidelines are presented to meet ITRS specification at 65 and 45 nm nodes. Optimal design of lateral source/drain doping profile can not only effectively control short channel effects, yielding low off-current, but also achieve low values of intrinsic gate delay.

Probabilistic nonlocal gate operation via imperfect entanglement

Nonlocal gate operation is based on sharing an ancillary pair of qubits in perfect entanglement. When the ancillary pair is partially entangled, the efficiency of gate operation drops. Using general transformations, we devise probabilistic nonlocal gates, which perform the nonlocal operation conclusively when the ancillary pair is only partially entangled. We show that a controlled purification protocol can be implemented by the probabilistic nonlocal operation.

Investigating the cost Performance of UK Credit Unions using Radial and Non-Radial Efficiency Measures

This paper examines the relative efficiency of UK credit unions. Radial and non-radial measures of input cost efficiency plus associated scale efficiency measures are computed for a selection of input output specifications. Both measures highlighted that UK credit unions have considerable scope for efficiency gains. It was mooted that the documented high levels of inefficiency may be indicative of the fact that credit unions, based on clearly defined and non-overlapping common bonds, are not in competition with each other for market share. Credit unions were also highlighted as suffering from a considerable degree of scale inefficiency with the majority of scale inefficient credit unions subject to decreasing returns to scale. The latter aspect highlights that the UK Government's goal of larger credit unions must be accompanied by greater regulatory freedom if inefficiency is to be avoided. One of the advantages of computing non-radial measures is that an insight into potential over- or under-expenditure on specific inputs can be obtained through a comparison of the non-radial measure of efficiency with the associated radial measure. Two interesting findings emerged, the first that UK credit unions over-spend on dividend payments and the second that they under-spend on labour costs.

Numerical and Experimental Study of the Performance Effects of Varying Vaneless Space and Vane Solidity in Radial Inflow Turbine Stators.

An extensive experimental program has been carried out on a 135?mm tip diameter radial turbine using a variety of stator designs, in order to facilitate direct performance comparisons of varying stator vane solidity and the effect of varying the vaneless space. A baseline vaned stator was designed using commercial blade design software, having 15 vanes and a vane trailing edge to rotor leading edge radius ratio (Rte/rle) of 1.13. Two additional series of stator vanes were designed and manufactured; one series having varying vane numbers of 12, 18, 24, and 30, and a further series with Rte/rle ratios of 1.05, 1.175, 1.20, and 1.25. As part of the design process a series of CFD simulations were carried out in order to guide design iterations towards achieving a matched flow capacity for each stator. In this way the variations in the measured stage efficiency could be attributed to the stator passages only, thus allowing direct comparisons to be made. Interstage measurements were taken to capture the static pressure distribution at the rotor inlet and these measurements were then used to validate subsequent numerical models. The overall losses for different stators have been quantified and the variations in the measured and computed efficiency were used to recommend optimum values of vane solidity and Rte/rle.

6-T SRAM cell design with nanoscale double-gate SOI MOSFETs: impact of source/drain engineering and circuit topology

The impact of source/drain engineering on the performance of a six-transistor (6-T) static random access memory (SRAM) cell, based on 22 nm double-gate (DG) SOI MOSFETs, has been analyzed using mixed-mode simulation, for three different circuit topologies for low voltage operation. The trade-offs associated with the various conflicting requirements relating to read/write/standby operations have been evaluated comprehensively in terms of eight performance metrics, namely retention noise margin, static noise margin, static voltage/current noise margin, write-ability current, write trip voltage/current and leakage current. Optimal design parameters with gate-underlap architecture have been identified to enhance the overall SRAM performance, and the influence of parasitic source/drain resistance and supply voltage scaling has been investigated. A gate-underlap device designed with a spacer-to-straggle (s/sigma) ratio in the range 2-3 yields improved SRAM performance metrics, regardless of circuit topology. An optimal two word-line double-gate SOI 6-T SRAM cell design exhibits a high SNM similar to 162 mV, I-wr similar to 35 mu A and low I-leak similar to 70 pA at V-DD = 0.6 V, while maintaining SNM similar to 30% V-DD over the supply voltage (V-DD) range of 0.4-0.9 V.