Design rationnel de nanothermomètres programmables à base d’ADN

Développer de nouveaux nanomatériaux, interrupteurs et machines nanométriques sensibles à de petites variations de température spécifiques devrait être de grande utilité pour une multitude de domaines œuvrant dans la nanotechnologie. De plus, l’objectif est de convaincre le lecteur que les nanotechnologies à base d’ADN offrent d’énormes possibilités pour la surveillance de température en temps réel à l’échelle nanométrique. Dans la section Résultats, nous exploitons les propriétés de l’ADN pour créer des thermomètres versatiles, robustes et faciles à employer. En utilisant une série de nouvelles stratégies inspirées par la nature, nous sommes en mesure de créer des nanothermomètres d’ADN capables de mesurer des températures de 25 à 95°C avec une précision de <0.1°C. En créant de nouveaux complexes d’ADN multimériques, nous arrivons à développer des thermomètres ultrasensibles pouvant augmenter leur fluorescence 20 fois sur un intervalle de 7°C. En combinant plusieurs brins d’ADN avec des plages dynamiques différentes, nous pouvons former des thermomètres montrant une transition de phase linéaire sur 50°C. Finalement, la vitesse de réponse et la précision des thermomètres développés et leur réversibilité sont illustrées à l’aide d’une expérience de surveillance de température à l’intérieur d’un unique puits d’un appareil de qPCR. En conclusion, les applications potentielles de tels nanothermomètres en biologie synthétique, imagerie thermique cellulaire, nanomachines d’ADN et livraison contrôlée seront considérées.

Constructive Synthesis of Memory-Intensive Accelerators for FPGA From Nested Loop Kernels

Field-programmable gate arrays are ideal hosts to custom accelerators for signal, image, and data processing but de- mand manual register transfer level design if high performance and low cost are desired. High-level synthesis reduces this design burden but requires manual design of complex on-chip and off-chip memory architectures, a major limitation in applications such as video processing. This paper presents an approach to resolve this shortcoming. A constructive process is described that can derive such accelerators, including on- and off-chip memory storage from a C description such that a user-defined throughput constraint is met. By employing a novel statement-oriented approach, dataflow intermediate models are derived and used to support simple ap- proaches for on-/off-chip buffer partitioning, derivation of custom on-chip memory hierarchies and architecture transformation to ensure user-defined throughput constraints are met with minimum cost. When applied to accelerators for full search motion estima- tion, matrix multiplication, Sobel edge detection, and fast Fourier transform, it is shown how real-time performance up to an order of magnitude in advance of existing commercial HLS tools is enabled whilst including all requisite memory infrastructure. Further, op- timizations are presented that reduce the on-chip buffer capacity and physical resource cost by up to 96% and 75%, respectively, whilst maintaining real-time performance.

FPGA-based soft-core processors for image processing applications

With security and surveillance, there is an increasing need to process image data efficiently and effectively either at source or in a large data network. Whilst a Field-Programmable Gate Array (FPGA) has been seen as a key technology for enabling this, the design process has been viewed as problematic in terms of the time and effort needed for implementation and verification. The work here proposes a different approach of using optimized FPGA-based soft-core processors which allows the user to exploit the task and data level parallelism to achieve the quality of dedicated FPGA implementations whilst reducing design time. The paper also reports some preliminary
progress on the design flow to program the structure. An implementation for a Histogram of Gradients algorithm is also reported which shows that a performance of 328 fps can be achieved with this design approach, whilst avoiding the long design time, verification and debugging steps associated with conventional FPGA implementations.

Time-Independent Discrete Gaussian Sampling for Post-Quantum Cryptography

As the development of a viable quantum computer nears, existing widely used public-key cryptosystems, such as RSA, will no longer be secure. Thus, significant effort is being invested into post-quantum cryptography (PQC). Lattice-based cryptography (LBC) is one such promising area of PQC, which offers versatile, efficient, and high performance security services. However, the vulnerabilities of these implementations against side-channel attacks (SCA) remain significantly understudied. Most, if not all, lattice-based cryptosystems require noise samples generated from a discrete Gaussian distribution, and a successful timing analysis attack can render the whole cryptosystem broken, making the discrete Gaussian sampler the most vulnerable module to SCA. This research proposes countermeasures against timing information leakage with FPGA-based designs of the CDT-based discrete Gaussian samplers with constant response time, targeting encryption and signature scheme parameters. The proposed designs are compared against the state-of-the-art and are shown to significantly outperform existing implementations. For encryption, the proposed sampler is 9x faster in comparison to the only other existing time-independent CDT sampler design. For signatures, the first time-independent CDT sampler in hardware is proposed. 

FPGA-based architecture for hyperspectral endmember extraction

Hyperspectral instruments have been incorporated in satellite missions, providing data of high spectral resolution of the Earth. This data can be used in remote sensing applications, such as, target detection, hazard prevention, and monitoring oil spills, among others. In most of these applications, one of the requirements of paramount importance is the ability to give real-time or near real-time response. Recently, onboard processing systems have emerged, in order to overcome the huge amount of data to transfer from the satellite to the ground station, and thus, avoiding delays between hyperspectral image acquisition and its interpretation. For this purpose, compact reconfigurable hardware modules, such as field programmable gate arrays (FPGAs) are widely used. This paper proposes a parallel FPGA-based architecture for endmember’s signature extraction. This method based on the Vertex Component Analysis (VCA) has several advantages, namely it is unsupervised, fully automatic, and it works without dimensionality reduction (DR) pre-processing step. The architecture has been designed for a low cost Xilinx Zynq board with a Zynq-7020 SoC FPGA based on the Artix-7 FPGA programmable logic and tested using real hyperspectral data sets collected by the NASA’s Airborne Visible Infra-Red Imaging Spectrometer (AVIRIS) over the Cuprite mining district in Nevada. Experimental results indicate that the proposed implementation can achieve real-time processing, while maintaining the methods accuracy, which indicate the potential of the proposed platform to implement high-performance, low cost embedded systems, opening new perspectives for onboard hyperspectral image processing.

A fast parallel hyperspectral coded aperture algorithm for compressive sensing using OpenCL

In this paper, we develop a fast implementation of an hyperspectral coded aperture (HYCA) algorithm on different platforms using OpenCL, an open standard for parallel programing on heterogeneous systems, which includes a wide variety of devices, from dense multicore systems from major manufactures such as Intel or ARM to new accelerators such as graphics processing units (GPUs), field programmable gate arrays (FPGAs), the Intel Xeon Phi and other custom devices. Our proposed implementation of HYCA significantly reduces its computational cost. Our experiments have been conducted using simulated data and reveal considerable acceleration factors. This kind of implementations with the same descriptive language on different architectures are very important in order to really calibrate the possibility of using heterogeneous platforms for efficient hyperspectral imaging processing in real remote sensing missions.

The Design and Implementation of a SD Card File System

SD card (Secure Digital Memory Card) is widely used in portable storage medium. Currently, latest researches on SD card, are mainly SD card controller based on FPGA (Field Programmable Gate Array). Most of them are relying on API interface (Application Programming Interface), AHB bus (Advanced High performance Bus), etc. They are dedicated to the realization of ultra high speed communication between SD card and upper systems. Studies about SD card controller, really play a vital role in the field of high speed cameras and other sub-areas of expertise. This design of FPGA-based file systems and SD2.0 IP (Intellectual Property core) does not only exhibit a nice transmission rate, but also achieve the systematic management of files, while retaining a strong portability and practicality. The file system design and implementation on a SD card covers the main three IP innovation points. First, the combination and integration of file system and SD card controller, makes the overall system highly integrated and practical. The popular SD2.0 protocol is implemented for communication channels. Pure digital logic design based on VHDL (Very-High-Speed Integrated Circuit Hardware Description Language), integrates the SD card controller in hardware layer and the FAT32 file system for the entire system. Secondly, the document management system mechanism makes document processing more convenient and easy. Especially for small files in batch processing, it can ease the pressure of upper system to frequently access and process them, thereby enhancing the overall efficiency of systems. Finally, digital design ensures the superior performance. For transmission security, CRC (Cyclic Redundancy Check) algorithm is for data transmission protection. Design of each module is platform-independent of macro cells, and keeps a better portability. Custom integrated instructions and interfaces may facilitate easily to use. Finally, the actual test went through multi-platform method, Xilinx and Altera FPGA developing platforms. The timing simulation and debugging of each module was covered. Finally, Test results show that the designed FPGA-based file system IP on SD card can support SD card, TF card and Micro SD with 2.0 protocols, and the successful implementation of systematic management for stored files, and supports SD bus mode. Data read and write rates in Kingston class10 card is approximately 24.27MB/s and 16.94MB/s.

Implementação em FPGA de um Modem QPSK

Esta dissertação insere-se num conjunto de trabalhos a decorrer no Instituto de Telecomunicações de Aveiro que tem como objetivo o desenvolvimento de um sistema de comunicação para um UAV. Neste sentido, apresenta a implementação e validação de um modem em banda base aberto e flexível implementado em FPGA, baseado em abordagem SDR, com possibilidade de integraçãoo no sistema de comunicação com o UAV. Ao longo desta dissertação implementou-se, utilizando o MATLAB, um modem de modulação adaptável, ao qual foram integrados algoritmos de sincronismo e de correção de fase. Desta forma, foi possível realizar uma análise ao modelo comportamental dos vários constituintes do modem abstraindose dos tempos de atraso do processamento ou da precisão da representação dos dados, e assim simplificar a sua implementação em hardware. Analisado o modelo comportamental do modem desenvolvido em MATLAB realizou-se a sua implementação em hardware para a modulação QPSK. A sua prototipagem foi realizada, com recurso à ferramenta computacional Vivado Design Suite 2014.2, utilizando o kit de desenvolvimento ZedBoard e o frontend AD-FMCOMMS1-EBZ. O correto funcionamento dos módulos implementados em hardware foi posteriormente avaliado através de uma interface entre o MATLAB e a Zed- Board, sendo que, os resultados obtidos no modelo em MATLAB serviram como termo de comparação. Através da utilização desta interface é possível validar parte do modem implementado em FPGA, mantendo o restante processamento a ser realizado em MATLAB, validando assim os módulos em FPGA de uma forma isolada.

EXTENDED-RANGE OBOE: THE IMPACT OF TECHNICAL AND MUSICAL ADVANCEMENTS IN 19th-CENTURY AND CONTEMPORARY OBOE REPERTOIRE

I believe that the purpose of expanding the oboe’s repertoire is to not only create original compositions, but to also utilize technical advancements in order to achieve access to a wider range of repertoire through the art of transcription. This paper examines the various paths to achieving such expansion, including utilizing unique performer skills, use of auxiliary instruments, advancements in the instrument itself and musical developments that challenge the perception of the oboe’s solo role in a particular era of music history. The oboe need not be relegated to the confines of a compositionally limited stereotype. The goal of my “extended-range” dissertation project is to expand the “range” of programmable repertoire, with a focus on music in both the 19th and 21st-centuries, while simultaneously expanding the technical capabilities and expectations of the modern oboe—in part by exploiting the new possibilities of the recently invented low-A extension key.

Operating infrastructure for an FPGA and ARM system

Advances in FPGA technology and higher processing capabilities requirements have pushed to the emerge of All Programmable Systems-on-Chip, which incorporate a hard designed processing system and a programmable logic that enable the development of specialized computer systems for a wide range of practical applications, including data and signal processing, high performance computing, embedded systems, among many others. To give place to an infrastructure that is capable of using the benefits of such a reconfigurable system, the main goal of the thesis is to implement an infrastructure composed of hardware, software and network resources, that incorporates the necessary services for the operation, management and interface of peripherals, that coompose the basic building blocks for the execution of applications. The project will be developed using a chip from the Zynq-7000 All Programmable Systems-on-Chip family.

MOLECULAR MASS MANIPULATION ENABLED BY GRAPHENE BASED NANOSTRUCTURES

The surge of interest in graphene, as epitomized by the Nobel Prize in Physics in 2010, is attributed to its extraordinary properties. Graphene is ultrathin, mechanically tough, and has amendable surface chemistry. These features make graphene and graphene based nanostructure an ideal candidate for the use of molecular mass manipulation. The controllable and programmable molecular mass manipulation is crucial in enabling future graphene based applications, however is challenging to achieve. This dissertation studies several aspects in molecular mass manipulation including mass transportation, patterning and storage. For molecular mass transportation, two methods based on carbon nanoscroll are demonstrated to be effective. They are torsional buckling instability assisted transportation and surface energy induced radial shrinkage. To achieve a more controllable transportation, a fundamental law of direction transport of molecular mass by straining basal graphene is studied. For molecular mass patterning, we reveal a barrier effect of line defects in graphene, which can enable molecular confining and patterning in a domain of desirable geometry. Such a strategy makes controllable patterning feasible for various types of molecules. For molecular mass storage, we propose a novel partially hydrogenated bilayer graphene structure which has large capacity for mass uptake. Also the mass release can be achieved by simply stretching the structure. Therefore the mass uptake and release is reversible. This kind of structure is crucial in enabling hydrogen fuel based technology. Lastly, spontaneous nanofluidic channel formation enabled by patterned hydrogenation is studied. This novel strategy enables programmable channel formation with pre-defined complex geometry.

Minimalist Hardware Architectures for Agent Tracking and Guidance

The philosophy of minimalism in robotics promotes gaining an understanding of sensing and computational requirements for solving a task. This minimalist approach lies in contrast to the common practice of first taking an existing sensory motor system, and only afterwards determining how to apply the robotic system to the task. While it may seem convenient to simply apply existing hardware systems to the task at hand, this design philosophy often proves to be wasteful in terms of energy consumption and cost, along with unnecessary complexity and decreased reliability. While impressive in terms of their versatility, complex robots such as the PR2 (which cost hundreds of thousands of dollars) are impractical for many common applications. Instead, if a specific task is required, sensing and computational requirements can be determined specific to that task, and a clever hardware implementation can be built to accomplish the task. Since this minimalist hardware would be designed around accomplishing the specified task, significant reductions in hardware complexity can be obtained. This can lead to huge advantages in battery life, cost, and reliability. Even if cost is of no concern, battery life is often a limiting factor in many applications. Thus, a minimalist hardware system is critical in achieving the system requirements. In this thesis, we will discuss an implementation of a counting, tracking, and actuation system as it relates to ergodic bodies to illustrate a minimalist design methodology.

Arquitetura híbrida com DSP e FPGA para implementação de controladores de filtros ativos de potência

The presence of non-linear loads at a point in the distribution system may deform voltage waveform due to the consumption of non-sinusoidal currents. The use of active power filters allows significant reduction of the harmonic content in the supply current. However, the processing of digital control structures for these filters may require high performance hardware, particularly for reference currents calculation. This work describes the development of hardware structures with high processing capability for application in active power filters. In this sense, it considers an architecture that allows parallel processing using programmable logic devices. The developed structure uses a hybrid model using a DSP and an FPGA. The DSP is used for the acquisition of current and voltage signals, calculation of fundamental current related controllers and PWM generation. The FPGA is used for intensive signal processing, such as the harmonic compensators. In this way, from the experimental analysis, significant reductions of the processing time are achieved when compared to traditional approaches using only DSP. The experimental results validate the designed structure and these results are compared with other ones from architectures reported in the literature.

Implementação em FPGA de compensadores de desvios para conversor analógico digital intercalado

This work presents the modeling and FPGA implementation of digital TIADC mismatches compensation systems. The development of the whole work follows a top-down methodology. Following this methodology was developed a two channel TIADC behavior modeling and their respective offset, gain and clock skew mismatches on Simulink. In addition was developed digital mismatch compensation system behavior modeling. For clock skew mismatch compensation fractional delay filters were used, more specifically, the efficient Farrow struct. The definition of wich filter design methodology would be used, and wich Farrow structure, required the study of various design methods presented in literature. The digital compensation systems models were converted to VHDL, for FPGA implementation and validation. These system validation was carried out using the test methodology FPGA In Loop . The results obtained with TIADC mismatch compensators show the high performance gain provided by these structures. Beyond this result, these work illustrates the potential of design, implementation and FPGA test methodologies.

Design and construction of a two dimensional duct equipped with a wave generator and a variable coastal slope and an ocean wave energy conversion system (OWC)

The aims of this thesis were evaluation the type of wave channel, wave current, and effect of some parameters on them and identification and comparison between types of wave maker in laboratory situations. In this study, designing and making of two dimension channels (flume) and wave maker for experiment son the marine buoy, marine building and energy conversion systems were also investigated. In current research, the physical relation between pump and pumpage and the designing of current making in flume were evaluated. The related calculation for steel building, channels beside glasses and also equations of wave maker plate movement, power of motor and absorb wave(co astal slope) were calculated. In continue of this study, the servo motor was designed and applied for moving of wave maker’s plate. One Ball Screw Leaner was used for having better movement mechanisms of equipment and convert of the around movement to linear movement. The Programmable Logic Controller (PLC) was also used for control of wave maker system. The studies were explained type of ocean energies and energy conversion systems. In another part of this research, the systems of energy resistance in special way of Oscillating Water Column (OWC) were explained and one sample model was designed and applied in hydrolic channel at the Sheikh Bahaii building in Azad University, Science and Research Branch. The dimensions of designed flume was considered at 16 1.98 0. 57 m which had ability to provide regular waves as well as irregular waves with little changing on the control system. The ability of making waves was evaluated in our designed channel and the results were showed that all of the calculation in designed flume was correct. The mean of error between our results and theory calculation was conducted 7%, which was showed the well result in this situation. With evaluating of designed OWC model and considering of changes in the some part of system, one bigger sample of this model can be used for designing the energy conversion system model. The obtained results showed that the best form for chamber in exit position of system, were zero degree (0) in angle for moving below part, forty and five (45) degree in front wall of system and the moving forward of front wall keep in two times of height of wave.