981 resultados para Java SIM Card
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Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)
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Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)
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Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)
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Smart card applications represent a growing market. Usually this kind of application manipulate and store critical information that requires some level of security, such as financial or confidential information. The quality and trustworthiness of smart card software can be improved through a rigorous development process that embraces formal techniques of software engineering. In this work we propose the BSmart method, a specialization of the B formal method dedicated to the development of smart card Java Card applications. The method describes how a Java Card application can be generated from a B refinement process of its formal abstract specification. The development is supported by a set of tools, which automates the generation of some required refinements and the translation to Java Card client (host) and server (applet) applications. With respect to verification, the method development process was formalized and verified in the B method, using the Atelier B tool [Cle12a]. We emphasize that the Java Card application is translated from the last stage of refinement, named implementation. This translation process was specified in ASF+SDF [BKV08], describing the grammar of both languages (SDF) and the code transformations through rewrite rules (ASF). This specification was an important support during the translator development and contributes to the tool documentation. We also emphasize the KitSmart library [Dut06, San12], an essential component of BSmart, containing models of all 93 classes/interfaces of Java Card API 2:2:2, of Java/Java Card data types and machines that can be useful for the specifier, but are not part of the standard Java Card library. In other to validate the method, its tool support and the KitSmart, we developed an electronic passport application following the BSmart method. We believe that the results reached in this work contribute to Java Card development, allowing the generation of complete (client and server components), and less subject to errors, Java Card applications.
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This work presents JFLoat, a software implementation of IEEE-754 standard for binary floating point arithmetic. JFloat was built to provide some features not implemented in Java, specifically directed rounding support. That feature is important for Java-XSC, a project developed in this Department. Also, Java programs should have same portability when using floating point operations, mainly because IEEE-754 specifies that programs should have exactly same behavior on every configuration. However, it was noted that programs using Java native floating point types may be machine and operating system dependent. Also, JFloat is a possible solution to that problem
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This dissertation aims at extending the JCircus tool, a translator of formal specifications into code that receives a Circus specification as input, and translates the specification into Java code. Circus is a formal language whose syntax is based on Z s and CSP s syntax. JCircus generated code uses JCSP, which is a Java API that implements CSP primitives. As JCSP does not implement all CSP s primitives, the translation strategy from Circus to Java is not trivial. Some CSP primitives, like parallelism, external choice, communication and multi-synchronization are partially implemented. As an aditional scope, this dissertation will also develop a tool for testing JCSP programs, called JCSPUnit, which will also be included in JCircus new version. The extended version of JCircus will be called JCircus 2.0.
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This work aims to develop modules that will increase the computational power of the Java-XSC library, and XSC an acronym for "Language Extensions for Scientific Computation . This library is actually an extension of the Java programming language that has standard functions and routines elementary mathematics useful interval. in this study two modules were added to the library, namely, the modulus of complex numbers and complex numbers of module interval which together with the modules original numerical applications that are designed to allow, for example in the engineering field, can be used in devices running Java programs
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The main goal of Regression Test (RT) is to reuse the test suite of the latest version of a software in its current version, in order to maximize the value of the tests already developed and ensure that old features continue working after the new changes. Even with reuse, it is common that not all tests need to be executed again. Because of that, it is encouraged to use Regression Tests Selection (RTS) techniques, which aims to select from all tests, only those that reveal faults, this reduces costs and makes this an interesting practice for the testing teams. Several recent research works evaluate the quality of the selections performed by RTS techniques, identifying which one presents the best results, measured by metrics such as inclusion and precision. The RTS techniques should seek in the System Under Test (SUT) for tests that reveal faults. However, because this is a problem without a viable solution, they alternatively seek for tests that reveal changes, where faults may occur. Nevertheless, these changes may modify the execution flow of the algorithm itself, leading some tests no longer exercise the same stretch. In this context, this dissertation investigates whether changes performed in a SUT would affect the quality of the selection of tests performed by an RTS, if so, which features the changes present which cause errors, leading the RTS to include or exclude tests wrongly. For this purpose, a tool was developed using the Java language to automate the measurement of inclusion and precision averages achieved by a regression test selection technique for a particular feature of change. In order to validate this tool, an empirical study was conducted to evaluate the RTS technique Pythia, based on textual differencing, on a large web information system, analyzing the feature of types of tasks performed to evolve the SUT
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This paper introduces Java applet programs for a WWW (world wide web)-HTML (hypertext markup language)-based multimedia course in Power Electronics. The applet programs were developed with the purpose of providing an interactive visual simulation and analysis of idealized uncontrolled single-phase, and three-phase rectifiers. In addition, this paper discusses the development and utilization of JAVA applet programs to solve some design-oriented equations for rectifier applications. The major goal of these proposed JAVA applets was to provide more facilities for the students increase their pace in Power Electronics course, emphasizing waveforms analysis, and providing conditions for an on-line comparative analysis among different hands-on laboratory experiences, via a normal Internet TCP/IP connection. Therefore, using the proposed JAVA applets, which were embedded in a WWW-HTML-based course in Power Electronics, was observed an important improvement of the apprenticeship for the content of this course. Therefore, the course structure becomes fluid, allowing a true on-line course over the WWW, motivating students to learn its content, and apply it in some applications-oriented projects, and their home-works.
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This paper presents Java applet programs for a WWW (world wide web)-HTML (hypertext markup language)-based multimedia course in basic power electronics circuits. These tools make use of the benefits of Java language to provide a dynamic and interactive approach to simulate steady-state idealized rectifiers (uncontrolled and controlled; single-phase and three-phase). In addition, this paper discusses the development and the use of the Java applet programs to assist the teaching of basics rectifier power electronics circuits, and to serve as a first design tool for basics power electronics circuits in the experiments of the laboratories. In order to validate the developed simulation applets, the results were confronted with results obtained from a well-know simulator package PSPICE. © 2005 IEEE.
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Reconfigurable computing is one of the most recent research topics in computer science. The Altera - Nios II soft-core processor can be included in a large set of reconfigurable architectures, especially because it is designed in software, allowing it to be configured according to the application. The recent growth in applications that demand reconfigurable computing made necessary the building of compilers that translate high level languages source codes into reconfigurable devices instruction sets. In this paper we present a compiler that takes as input the bytecodes generated by a Java front-end compiler and generates a set of instructions that attends to the Nios II processor instruction set rules. Our work shows how we process Java bytecodes to the intermediate code, in the Nios II instructions format, and build the control flow and the control dependence graphs. © 2009 IEEE.
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Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)
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Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)
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Pós-graduação em Engenharia Elétrica - FEIS
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Includes bibliography
